This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent VTH controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/dec). FDSOI can provide a valuable approach to cryogenic low-power electronics. Applications such as classical control hardware for quantum processors are envisioned.

For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve ION current improvement by 45% for LVT options at an IOFF current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um 2 bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔVT versus Vb ~ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances. IntroductionThin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the CET and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical threshold voltage (VT~0.45V) for both NMOS and PMOS devices [1], still one major challenge is to provide Multi-VT devices and dynamic VT modulation with an undoped channel in order to satisfy the low power (LP) circuit design requirements [2][3][4]. To overcome this issue, a simple and novel Multi-VT strategy has been proposed in [2], combining UTBOX substrate with different back plane (BP) and back biasing (Vb). This method based on single metal gate for process simplicity and cost saving is also very attractive thanks to the possibility to re-use the bulk forward (FBB)/reverse (RBB) biasing techniques. In this paper, the viability of this concept is demonstrated through silicon results across wafers in 45nm technology. Firstly, the electrical characteristics of the high-(HVT) standard-(SVT) and Low-(LVT) VT devices options are presented. Second, the RBB and FBB back biasing effectiveness for the static power and dynamic performance management is demonstrated on ring oscillators (RO) and 0.299µm 2 6T SRAM bitcells. Device fabrication and Multi-V T familiesThe FDSOI devices were processed on 300mm (100) UNIBOND TM SOI wafers with a buried oxide thickness of 10nm via the process flow scheme presented in Fig.2. The final silicon film thickness under the gate is 8nm, the nominal gate length is 40nm and the EOT 14Å (Fig.1). The use of UTBOX leads to further SCE improvement but has to be combined with a BP in order to suppress the depleted zone created under the BOX [5]. Fig.3 shows the three NMOS device VT configurations implemented in this study. For NMOS, the HVT and LVT options are based on a p-type BP set to 0V and ntype BP set to Vdd, respectively. The SVT option does not include BP and the back bias (Vb) is set to 0V. For the PMOS device, complementary BP doping type and biasing are applied [2]. All of these devices can be simply co-integrated in a circuit thanks to their configuration which avoids forward PN junctions in the substrate. The table in Fig.4a shows the electrical cha...

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For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (L eff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiplelevel stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H 2 anneal), the extracted coulomblimited mobility decreases whereas the surface roughnesslimited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

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