We report for the first time experimental investigations on SOI, Si 1-x Ge x OI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower I OFF (~30fA/µm) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET

No abstract

No abstract

No abstract

No abstract

No abstract

No abstract

Abstract-