Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Andrieu, F.; Ernst, T.; Lime, F.; Rochette, F.; Romanjek, K.; Barraud, S.; Ravit, C.; Bœuf, F.; Jurczak, M.; Cassé, M.; Weber, O.; Brévard, L.; Reimbold, G.; Ghibaudo, G.; Deleonibus, S.

doi:10.1109/.2005.1469257

Cited by 31 publications

(18 citation statements)

References 7 publications

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“…Scaling down of the buried oxide is mandatory to maintain the electrostatic characteristics of MOSFETs (Figure 6(a)) [25][26][27][28]. Recent results have shown that [29,30]; (b) strained dual channel CMOS process flow [29].…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 96%

“…A tensile Si and compressive SiGe dual strained channels on an insulator architecture has been demonstrated to be functional down to gate lengths of 15 nm (Figure 7) [29,30]. For sub-100-nm range channel lengths and widths, the strain induced by the nearby thin films affects the device characteristics [31].…”

Section: Boosting the Performances Of Complementary Mosfets By Strainmentioning

confidence: 98%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 96%

Section: Boosting the Performances Of Complementary Mosfets By Strainmentioning

confidence: 98%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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“…Optical phonon scattering [6], acoustic phonon confinement [7], Coulomb scattering at the buried oxide (BOX) interface [8], and t Si fluctuations [9] have been successively suggested to explain this undesired longchannel µ eff behavior. If strained channels are competitive candidates for mobility enhancement [10], strained µ eff degradation has also been observed when t Si decreases [11]. Moreover, strong electron and hole mobility degradation with gate length scaling has been widely demonstrated for both strained and unstrained MOSFETs [12]- [15].…”

Section: Introductionmentioning

confidence: 97%

Evidences on the Physical Origin of the Unexpected Transport Degradation in Ultimate n-FDSOI Devices

Barral

Poiroux

Barraud

et al. 2009

IEEE Trans. Nanotechnology

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International audienceDue to a new quasi-ballistic extraction methodology dedicated to low-longitudinal-field conditions, experimental carrier mean-free-paths have been determined on strained and un-strained fully depleted silicon-on-insulator (n-FDSOI) devices with Si film thickness ranging from 11.8 to 2.5 run, gate length down to 30 nm, and a TiN/HfO2 gate stack. Electron mobility evolution with the Si film thickness, reported in a previous study, is explored and quantitatively explained. Moreover, through inversion charge and temperature deep investigations, dominant carrier transport mechanisms are analyzed. It is experimentally revealed that transport degradation occurs in short and thin channels, which is shown to be mainly due to additional Coulomb scatterings rather than ballistic artifact in both strained and unstrained devices

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“…These techniques typically achieve performance boosts by increasing the amount of mechanical stress induced within a MOS-FET's channel. Applying mechanical stress to a MOSFET channel alters its valence and conduction bands, which results in changed carrier mobility and/or band scattering rates [1,2]. Increasing mobility by inducing stress counteracts mobility degradation and also increases the drain-to-source current (I DS ) in all device operating regimes.…”

Section: Introductionmentioning

confidence: 99%

STEEL: A technique for stress-enhanced standard cell library design

Joshi¹,

Sylvester²,

Blaauw³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobility which, consequently, increases both I on and I off in CMOS devices. However, most stress-enhancement techniques are dependent on layout parameters and their effects can be exploited within standard cell library design. In this work, we propose a new standard cell library design methodology that shares V DD and V SS source/drain connections across standard cell boundaries. Such sharing allows for increased channel stress in both the corresponding device as well as its neighboring devices. Using an industrial 65nm process and standard cell library, we show that our standard cell design methodology can be seamlessly integrated into current, state-of-the-art digital IC design flows. The new shared source/ drain technique improves critical path delay by 11% on average over a number of benchmarks for only a ~35% increase in leakage. Furthermore, stress-enhanced standard cell libraries offer a superior power/ delay tradeoff compared to dual-V th across a wide range of operating points with reduced manufacturing costs. Specifically, our stressenhanced library (with a single V th ) consumes ~2.5X less leakage than its dual-V th counterpart.

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Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Cited by 31 publications

References 7 publications

Ultra-thin films and multigate devices architectures for future CMOS scaling

Ultra-thin films and multigate devices architectures for future CMOS scaling

Evidences on the Physical Origin of the Unexpected Transport Degradation in Ultimate n-FDSOI Devices

STEEL: A technique for stress-enhanced standard cell library design

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