Ultra-thin films and multigate devices architectures for future CMOS scaling

Abstract

The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

“…For high aspect ratio MuG-FETs, the fully depleted channel could not be used for threshold voltage tunning. The V T adjustment could only be realized by the careful work function tunning of metal gate electrode [41] . Mid-gap metal like TiN could be used for both p-and n-channel MuGFETs to obtain a medium V T .…”

A quantum-confinement model for surrounding-gate MOSFETS from subthreshold to strong-inversion regions

“…Surrounding-gate (SG) nanowire MOSFETs are considered attractive candidates for future CMOS scaling as they offer the strongest gate control over the channel for suppression of short channel effects (SCEs) [1][2][3][4]. In addition to SCEs caused by the decreasing channel length, quantum confinement effects (QCEs) become more significant as the channel radius of SG nanowire transistors scales down [5,6].…”