Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

Abstract

For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (L eff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiplelevel stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H 2 anneal), the extracted coulomblimited mobility decreases whereas the surface roughnesslimited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

“…[1][2][3][4][5][6][7] The future may see the use of threedimensional (3D) MOSFETs, such as vertically stacked SiNW FETs, [8][9][10][11][12] for high device densities. An asymmetric channel structure is expected for the vertically stacked SiNW FETs because of the fabrication processes.…”

High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments

“…The three fitting coefficients are µ sr = 629 cm 2 /Vs, A = 2.38 × 10 6 cm 2 K 1.5 /Vs, and B = 2.42 × 10 6 cm 2 /K 1.5 Vs. As shown in Figure 11b, the device current in the linear region at two different temperatures was calculated using the mobility obtained by this model, and the modelling results are also in good agreement with the experimental results. It is worth mentioning that the mobility in our work is higher than that in GAA SNWTs with or without H 2 annealing [18] in Figure 11c, indicating that the inverted triangle cross section achieved by TMAH wet etching can effectively reduce the influence of surface roughness scattering.…”

Characterization of the electrical properties of advanced silicon-on-insulator (SOI) materials and transistors

“…Mobility can be measured by split C-V or Y-function methods. 45 Favorable mobility values have been reported in relatively wide nanowires (20 nm), in particular when strain was used as a booster. Carrier mobility is systematically lower than in planar FD MOSFETs with equivalent thickness.…”