Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Abstract

This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration

“…Regarding SCE, a recent report 13 showed that measurement results for the fabricated WSND AG SNWFET had lower DIBL than that for NSWD, in contrast to our results. However, this could be induced by the difference in L G (for our device, L G ¼ 20 nm; in Ref.…”

“…However, this could be induced by the difference in L G (for our device, L G ¼ 20 nm; in Ref. 13, L G was over 100 nm) and the structural constitution of the junction between the channel and source/drain, since the channel length and junction play important roles in DIBL behavior. At this point, an additional analysis on the effect of the junction constitution is needed rather than a direct comparison to the result of Ref.…”

“…At this point, an additional analysis on the effect of the junction constitution is needed rather than a direct comparison to the result of Ref. 13. Therefore, in the following section III B, the change in electric characteristics due to the doping concentration profile at the source/drain is investigated to determine the feasibility of performance enhancement in the case of WSND AG SNWFET.…”

“…[8][9][10][11][12] However, it has been reported that an asymmetric channel structure with inhomogeneous width should be expected for vertically stacked SNWFETs fabricated using a conventional top-down process. 13 In the previous studies, the electrical properties of FinFETs and Double Gate FETs (DGFETs) with an asymmetric channel have been investigated using experimental and simulation methods; 14,15 however, to date these studies have not been performed for GAA SNWFETs.…”

Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

“…12,13) The electrical variations caused by random dopant and line-edge roughness in fabrication processes have been studied in order to understand the electrical fluctuations of TFETs, 14) where the asymmetrical channel thickness or diameter from the variability of the fabrication process can mainly cause electrical fluctuations in nanometer regimes. 15) For conventional and junctionless nanowire FETs, technical computer-aided design (TCAD) simulations using thermionic diffusion transport have shown that the asymmetric gate controllability of the source and drain junctions largely affect the device performance. 16,17) Depending on the channel thickness of the source or drain side, the on=off-current and subthreshold swing can be enhanced or degraded in the nanowire FETs.…”