28nm Fully-depleted SOI technology: Cryogenic control electronics for quantum computing

Abstract

This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent VTH controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/dec). FDSOI can provide a valuable approach to cryogenic low-power electronics. Applications such as classical control hardware for quantum processors are envisioned.

Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

“…Since the scattering of charge carriers with phonons is sufficiently weak and can be neglected at liquid helium temperature, electron and hole mobilities are enhanced and should lead to a smaller t p at lower temperature for a given V DD . However, despite a significant increase of drive current expected at low temperature [18], the RO slows down as it can be seen in Fig. 3a.…”

“…In order to preserve the benefit of higher carrier mobility and thus, higher driving current at low temperatures, the V TH -shift should be compensated. The ability to adjust V TH through backbiasing was already successfully demonstrated down to 4.3K using 28nm FD-SOI transistors [18]. In this work, the threshold voltages of n-and p-MOSFET as well as the body-factors (DV TH /DV FBB ) were systematically extracted over a wide range of V FBB from 0 up to 3V.…”

“…The GO1 FD-SOI transistors are fabricated with a gate-first high-κ metal gate using STMicroelectronics technology [17][18]. They are processed on 300mm (100) SOI wafers with a buried oxide (BOX) thickness of 25nm.…”

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

“…Furthermore, accounting for the hopping current leads to a SS theory that explains the measured SS roll-off from room down to sub-Kelvin temperature [81]. Besides the saturation of the subthreshold slope, oscillations in weak inversion have been measured in the current characteristics of some devices fabricated in advanced and mature CMOS technologies [74], [76], [83]. These oscillations are most prominent at low drain bias (in the order of 1-10 mV) and temperatures lower than ≈ 36 K. Simoen et al hint at a resonant tunneling current to be responsible for this phenomenon [83].…”

“…Yet, a string of consecutive interface states in the channel can form a sequence of potential barriers between source and drain, and thus an accidental superlattice is established through which minority carriers can resonantly tunnel. Other defects than interface traps with active energies close to a band edge should also be considered for that purpose (e.g., dopants diffused unintentionally from the source and drain contacts into the channel [74], [88]). Above, we have discussed the current components in weak inversion (drift, diffusion, hopping, and resonant tunneling).…”