A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

Jazaeri, Farzan; Beckers, Arnout; Tajalli, Armin; Sallèse, Jean-Michel

doi:10.23919/mixdes.2019.8787164

Cited by 80 publications

(34 citation statements)

References 94 publications

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“…Furthermore, the physics definition of V T as used in textbooks, which normally corresponds to the gate voltage at two times the bulk Fermi potential at room temperature, will have to be revised at cryogenic temperatures due to dopant freezeout in the substrate [28], [29]. Finally, the presented results on the temperature behavior of V T are important for the modeling, reliability studies, and optimization of commercial CMOS processes for cryogenic operation, which is timely for the development of quantum computation systems [30]- [37].…”

Section: Introductionmentioning

confidence: 99%

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Beckers

Jazaeri

Grill

et al. 2020

IEEE J. Electron Devices Soc.

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This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOSspecific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

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Section: Introductionmentioning

confidence: 99%

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Beckers

Jazaeri

Grill

et al. 2020

IEEE J. Electron Devices Soc.

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“…The PLL/PLO therefore appears to be an interesting candidate radiofrequency source for a quantum microprocessor [10,11]. A survey of the recent literature reveals that, under the pressure of packing together a large number of qubits, being the estimated goal for the quantum supremacy in the range of tens of millions, the actual envisage solution is moving the classical CMOS circuitry closer to the qubits by levering on the actual microelectronics technology [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. The design of cryogenic CMOS circuitry for a quantum microprocessor is a real multi-faceted activity covering RFIC [12,17,22,24,26], DAC [16,24,26], readout circuits [22,25], and more general aspects related to the microprocessor architecture [15,23,25] and to the cryogenic system, as well.…”

Section: Pll/plo and Quantum Microprocessorsmentioning

confidence: 99%

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

2021

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The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthesize control signals for spintronic qubits. In a quantum microprocessor, these circuits should operate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been systematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physical models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guidelines for the VCO/FD interface, useful in the absence of cryogenic DKs.

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“…Apart from the superconductivity, the spins of the electron (spin-up and spin-down, irrespective of the convention), the polarization of a photon (vertical and horizontal polarization, irrespective of the convention), etc. can be used to physically realize a qubit [47]. Figure 2.9: Not gate and the corresponding truth table [4].…”

Section: Physical Implementationmentioning

confidence: 99%