Abstract-This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 mm CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-lowcutoff-frequency MOSFET-C filter.Introduction: Integrated high-value resistors (HVR) are key elements in many applications. Compact HVRs can be applied for biasing purposes or for implementing very-low-frequency filters [1,2]. In addition to achieving high resistance, usually it is necessary to have good tuning capability of the resistor value, thus the controllability of the HVR is another important design issue. In this Letter, a compact HVR is introduced that utilises only PMOS transistors operating in the subthreshold regime. The resistance is adjustable in a very wide range. This property makes this technique very suitable for ultra-low-power reconfigurable applications. A test chip has been fabricated in conventional 0.18 mm CMOS technology and characterised to verify this concept. The proposed HVR has been applied to implement a low-frequency MOSFET-C filter with a wide tuning range and a constant dynamic range (DR).

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Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is currently way ahead of all other qubit implementations. This paper briefly reviews the progress made on the silicon-based QC platform, which is highly promising to meet the scale-up challenges by leveraging the semiconductor industry. We look at different types of qubits, the advantages of silicon, and techniques for qubit manipulation in the solid state. Finally, we discuss the possibility of co-integrating silicon qubits with FET-based, cooled front-end electronics, and review the device physics of MOSFETs at deep cryogenic temperatures.