Abstract-This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 mm CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-lowcutoff-frequency MOSFET-C filter.Introduction: Integrated high-value resistors (HVR) are key elements in many applications. Compact HVRs can be applied for biasing purposes or for implementing very-low-frequency filters [1,2]. In addition to achieving high resistance, usually it is necessary to have good tuning capability of the resistor value, thus the controllability of the HVR is another important design issue. In this Letter, a compact HVR is introduced that utilises only PMOS transistors operating in the subthreshold regime. The resistance is adjustable in a very wide range. This property makes this technique very suitable for ultra-low-power reconfigurable applications. A test chip has been fabricated in conventional 0.18 mm CMOS technology and characterised to verify this concept. The proposed HVR has been applied to implement a low-frequency MOSFET-C filter with a wide tuning range and a constant dynamic range (DR).

We present a novel demonstration of real-time dynamic interaction between an oscillatory spinal cord (isolated lamprey nervous system) and electronic hardware that mimics the spinal motor pattern generating circuitry. The spinal cord and the neuromorphic circuit were interfaced in unidirectional and bidirectional modes. Bidirectional coupling resulted in stable, persistent oscillations. This experimental platform offers a unique paradigm to examine the intrinsic dynamics of neural circuitry. The neuromorphic analog very large scale integration (aVLSI) design and real-time capabilities of this approach may provide a particularly powerful means of restoring complex neuromotor function using neuroprostheses.

Abstract-This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 µm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18 mm CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1 nA, achieving sufficiently high gain ( > 3) over a wide frequency range.Introduction: Current-mode logic (CML) circuits are widely used in many high-speed and high-performance applications [1]. The differential topology of CML circuits provides high immunity to supply noise and crosstalk, while reduced voltage swing at the output helps to operate the circuit in very high frequencies with low noise generation [1,2]. These properties make the MOS CML (MCML) topology an attractive candidate for ultra-low power applications as well. This, however, usually requires that the circuit be biased in the subthreshold region, conducting a very low tail current and still producing a sufficiently large output swing. While several techniques for implementing CMOS logic circuits with transistors in the subthreshold regime and with very low power dissipation have been already introduced [3], the design of ultra-low power MCML circuits is yet an open research subject. This Letter introduces a new approach for implementing MCML circuits that can be applied to digital CMOS technologies.