Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Tajalli, Armin; Brauer, E.J.; Leblebici, Yusuf; Vittoz, E.A.

doi:10.1109/jssc.2008.922709

Cited by 105 publications

(81 citation statements)

References 25 publications

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“…Its roots derive from the design of analog circuits used within the first electronic watches. The model has been used primarily in the design of low power analog circuits, but it also finds application in digital logic [20]. For a thorough presentation of its influential history see [21].…”

Section: Static Cmosmentioning

confidence: 99%

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Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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Ajoitusvirheentunnistus (TED) mahdollistaa energian kulutuksen vähentämisen mikroprosessoreissa. Tässä diplomityössä on kaksi versiota ajoitusvirheentunnistavasta salvasta (esim. TDTBsubI ja TDTBsubII) ja systeemitason testipiiri (SystemTest), joka käyttää TDTBsub salpaa, mikä on suunniteltu toimimaan kynnysalueen alapuolella. Diplomityö esittelee ensin dynaamisen jännitteen skaalauksen (DVS), koska TED käytetään sellaisissa järjestelmissä. Seuraavaksi esitellään teoriaa kynnysalueen alapuolen suunnittelun haasteista. Sitten esitellään molempien TDTBsub salpojen ja SystemTest-lohkojen suunnittelu. Simulaatiotuloksia esitellään keskittyen operaatiotaajuuteen, energian kulutukseen ja toimintavarmuuteen variaatiot huomioon ottaen. Operoitaessa kynnysalueen alapuolella TDTB-piirillä keskityttiin koon mitoittamiseen ja suunnittelutyyliin. Ennen kaikkea kaikkien komponenttien mitoituksen piti olla suurempi kuin minimi CMOS-tekniikan leveydet. Vaikka mitoittamisella saavutettiin toimintavarmuutta kynnysalueen alapuolella toimittaessa myös energian kulutus kasvoi siellä toimittaessa. Perinteisiä vuotovirtojen vähentäviä mitoitustoimenpiteitä tehtiin suurimmalle osalle komponenteista. Logiikkatyyli on tärkeää kynnysalueen alapuolella operoitaessa. TDTBsubII salvassa uuden tekniikan näytetään antavan systeemitason suorituskykyä. Simulaatioilla näytettiin kuinka ajoitusvirheentunnistus kykeni toimimaan kynnystason alapuolella. TDTBsubI:n ja yhteenlaskun testipiirin piirinkuvio tehtiin 65nm CMOS-prosessilla. TDTBsubII salpaa ei tehty, koska se suunniteltiin piirin määräajan jälkeen. Piiriä tarkasteltaessa osoittautui, että piiri ei toiminut. Piirin toimimattomuus johtui tuotantovaiheessa tapahtuneesta virheestä eikä suunnittelusta. Avainsanat:sub-threshold,weak inversion,low power,low voltage,digital CMOS To operate TDTBsub into sub-threshold, attention was given to sizing and logic style. In general, the sizing of all components was required to be larger than the minimum CMOS width. Although this provided robustness in sub-threshold, the energy consumption in above sub-threshold was much higher. General leakage reduction sizing techniques were also applied to the majority of components. The choice of logic style is important for sub-threshold operation. In the TDTBsubII latch, a new technique is shown to provide system-level capability. Simulations displayed the capability of TED in sub-threshold. The layout of TDTBsubI and an adder test circuit were constructed in 65 nm CMOS. The TDTBsubII latch was not built since it was designed after the chip deadline. Upon inspection of the chip, it was determined to be inoperative. This mistake was a result of the manufacturering process and not the design in this work. Keywords:sub-threshold, weak inversion, low power, low voltage, digital CMOS ii ForewordThe work for this thesis was carried out at the Electronic Circuit Design Laboratory (ECDL) of TKK. The financial support of this project was provided by the Academy of Finland. The project was coordinated with University of Turku ...

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Section: Static Cmosmentioning

confidence: 99%

“…For stacks of CMOS devices, (3.4) is particularly useful in providing a first-order hand calculation to understand the operation. It has proved to be useful for operation of digital circuits in sub-threshold [20].…”

Section: Static Cmosmentioning

confidence: 99%

Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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“…2. Measurements show that the tail bias current of each cell can be selected in the range of 10pA < I SS < 200nA with a supply voltage of as low as 350mV [14].…”

Section: Ultra Low Power Source-coupled Logicmentioning

confidence: 99%

“…Some recent developments have shown that it is possible to use this topology for ultra low power applications [13], [14]. Subthreshold SCL (STSCL) circuits can operate with a very low bias current per cell (down to few pA) and still provide a low sensitivity to the supply voltage.…”

Section: Introductionmentioning

confidence: 99%

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Tajalli

Alioto

Brauer

et al. 2009

Lecture Notes in Computer Science

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Abstract. Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18µm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

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“…Various methods and techniques, such as voltage scaling, clock gating, etc. [1][2][3] have been applied successfully in the medium power, medium performance region of the design spectrum for lower power consumption. Nevertheless, in some applications where ultra-low power consumption is the primary requirement and performance is of secondary importance, a more aggressive approach is warranted.…”

Section: Introductionmentioning

confidence: 99%

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Rai¹,

Mishra²,

Tiwari³

2013

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This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 µm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

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Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Cited by 105 publications

References 25 publications

Sub-threshold operation of a timing error detection latch

Sub-threshold operation of a timing error detection latch

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

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