The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.
I. INTRODUCTIONTechnology scaling has traditionally enabled circuits to operate at better energy efficiency than the previous generation. While this still holds true for high-performance circuits operating near the nominal supply voltage, the increased proportion of leakage power has become a limiting factor in energy reduction for systems employing low supply voltage. As pointed in [1], recent manufacturing processes require custom-tailored standard cells to operate efficiently and reliably near the minimum energy point (MEP), where process and environment variations have great impact.In this paper, we show a method of operating logic reliably at the MEP using standard cells from the silicon provider, removing much of the overhead of custom cell design. We have implemented a 32-bit RISC CPU in 28nm CMOS, which has its energy-optimal point at near-threshold supply voltage. To minimize energy-consuming safety margins, we have utilized timing-error prevention (TEP) with adaptive clocking. TEP is a version of timing-error detection (TED) [2] [3] which has been shown to be effective in largely removing variation-incurred timing margins. The TED methodology is based on having the system operate at a voltage and frequency point in which the timing of critical paths fails intermittently. These failed timing occurrences are detected and handled (by instruction replay, etc.), whereas TEP uses adaptive margining to prevent the errors, thereby simplifying the handling process.TEP methodology and its integration to our design is elaborated in Section II. In Section III, we present system simulations which demonstrate the benefits of TEP. Finally, test chip measurements are presented in Section IV.
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm 2 , and operates down to 300 mV.
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