Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing

Paz, Bruna Cardoso; Guevel, L. Le; Cassé, M.; Billiot, G.; Pillonnet, Gaël; Jansen, A. G. M.; Maurand, Romain; Haendler, S.; Juge, André; Galy, Philippe; Ghibaudo, G.; Vinet, M.; Franceschi, S. De; Meunier, Tristan; Gaillard, F.

doi:10.1109/vlsitechnology18217.2020.9265034

Cited by 26 publications

(12 citation statements)

References 5 publications

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“…The greater enhancement for the pMOS is due to the steeper SS exhibited by these devices at 4.6 K. While the increase of ION at 4.6 K is impressive and could be leveraged for tailored cryogenic CMOS with lower VDD, the shift in VT must be accounted for through design of an ultra-high-VT technology. In addition, the VT variability, must be accounted for and will limit the smallest value of SS that can be leveraged [9].…”

Section: Resultsmentioning

confidence: 99%

“…The realization of such a technology would enable cryogenic electronics with extremely low power dissipation, that could support quantum computers with very large number of qubits. [17] nMOS 20 160 22 % (0.9 V) --28 nm FD-SOI [9] nMOS 5 160 ----40 nm bulk CMOS [18] nMOS 28 120 13% (1.1 V) 3.5x (0.6 V) 160 nm bulk CMOS [18] nMOS 23 150 67% (1.8 V) 3x (0.6 V)…”

Section: Discussionmentioning

confidence: 99%

“…With a few Watts of available power at 3 K, this places a limit on the number of qubits that can be supported with such electronics. To enable cryogenic ICs with even lower operating power, leveraging the unique features of the cryogenic operation of CMOS transistors is a promising approach [9]. These features include steeper turn on/off characteristics, i.e.…”

Section: Introductionmentioning

confidence: 99%

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Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Chabane

Prathapan

Mueller

et al. 2021

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

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In this work, we report characterization and modeling of 14 nm bulk FinFET technology from roomtemperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The nMOS device showed satured subthreshold swing of 20 mV/decade, VT shift of 80 mV and gm enhancement of 30%, all at 4.6 K. These results show that a tailored cryogenic FinFET technology, i.e. one accounting for the change in VT and SS, could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology could have strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Chabane

Prathapan

Mueller

et al. 2021

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

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“…The ultra-thin body and buried-oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS platform is a potential platform for both of the above-mentioned cryogenic RF application, due to high transistor density, low power dissipation, reduced parasitic and optimized RF performance [6], [7]. Commercially available FDSOI CMOS technologies (22nm, 28nm node) has been investigated in detail down to 4.2K, along with self-heating effects [8] and device variability [9]. However, these studies mainly evaluated the temperature dependence of MOSFET DC parameters, like thresholdvoltage, sub-threshold swing, transconductance and drivecurrent.…”

Section: Introductionmentioning

confidence: 99%

Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS

Chakraborty

Aabrar

Gomez

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Analog and RF mixed-signal cryogenic-CMOS circuits with ultra-high gain-bandwidth product can address a range of applications such as interface circuits between Superconducting Single-flux Quantum (SFQ) logic and cryo-DRAM memory, circuits for sensing and controlling qubits faster than their de-coherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18nm gate length (LG) FDSOI NMOS and PMOS from 300K to 5.5K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency (fT) of 495/337 GHz (1.35x /1.25x gain over 300K) and peak maximum oscillation frequency (fMAX) of 497/372 GHz (1.3x gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperatureinvariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.

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“…Therefore, technology optimization is compelling to make such approach feasible. In fact, characterization and modeling of MOS devices at deep cryogenic temperatures are mostly performed on mature technologies [8] [9] [10] [11]. Moreover, to the best of our knowledge, no characterization or compact model has ever been developed for multi-gate structures like the one presented in this work.…”

Section: Introductionmentioning

confidence: 99%

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

Catapano

Ghibaudo

Cassé

et al. 2021

IEEE J. Electron Devices Soc.

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This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Yfunction method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

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Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing

Cited by 26 publications

References 5 publications

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS

Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature

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