In this work, we report characterization and modeling of 14 nm bulk FinFET technology from roomtemperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The nMOS device showed satured subthreshold swing of 20 mV/decade, VT shift of 80 mV and gm enhancement of 30%, all at 4.6 K. These results show that a tailored cryogenic FinFET technology, i.e. one accounting for the change in VT and SS, could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology could have strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

In this work, we report characterization and modeling of 14 nm bulk FinFET technology from roomtemperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The nMOS device showed satured subthreshold swing of 20 mV/decade, VT shift of 80 mV and gm enhancement of 30%, all at 4.6 K. These results show that a tailored cryogenic FinFET technology, i.e. one accounting for the change in VT and SS, could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology could have strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

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