Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Abstract

In this work, we report characterization and modeling of 14 nm bulk FinFET technology from roomtemperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The nMOS device showed satured subthreshold swing of 20 mV/decade, VT shift of 80 mV and gm enhancement of 30%, all at 4.6 K. These results show that a tailored cryogenic FinFET technology, i.e. one accounting for the change in VT and SS, could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology could have strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

Cryogenic Embedded System to Support Quantum Computing: From 5-nm FinFET to Full Processor

“…Authors in [19], [20] showed that transistors fabricated using 160 nm and 40 nm bulk CMOS technologies result in an almost equal amount of performance improvement. However, the 40 nm technology with higher gate control and improved short-channel effects outperforms the older generation technologies at both 300 K and 4 K. [21], [22] showed that FinFETs from both 14 nm and 10 nm technologies can offer a significant power reduction while operating at cryogenic temperatures for a similar speed. A detailed study on the impact of ionized donor impurity on 10 nm technology node-based transistors suggests that direct transport through individual dopants results in a higher leakage current [23], [24].…”

“…However, in our measurements, we have not observed the impact of resonant tunneling due to ionized dopants. Although [21], [22] reported the FinFETs cryogenic characterization, these studies were limited up to 77 K. [25] presented the 16 nm FinFET cryogenic characterization from 2.5 K to 300 K. In our previous work [26], we have characterized 5 nm FinFET technology at 300 K and 10 K.…”

Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing

“…FIGURE 5(a) and FIGURE 5(b) present the validation of full IV characteristics for both n/p-FinFET at the room temperature (RT) and at cryogenic temperatures, i.e, 77K, for our 14nm FinFET experimental data. The model is further validated for 14nm IBM FinFET data [12] at different temperatures, as shown in FIGURE 5(c). We adjust the parameters in the temperature dependent model parameters, such as sub-threshold slope, threshold voltage, effective mobility and velocity saturation effect, such that both ON and OFF characteristics of the device are captured accurately at different temperatures using a single set of model cards.…”