Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

Abstract

In this work, we report characterization and modeling of 14 nm bulk FinFET technology from roomtemperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The nMOS device showed satured subthreshold swing of 20 mV/decade, VT shift of 80 mV and gm enhancement of 30%, all at 4.6 K. These results show that a tailored cryogenic FinFET technology, i.e. one accounting for the change in VT and SS, could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology could have strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control

“…At 4 K the measured signal shows larger signal amplitude when compared to the same measurement at room temperature and 77 K (not shown in the figure). The effect could be attributed to a combined effect of increase in the device drain saturation current for a given applied potential [6] and reduced cable losses in the dip stick. To perform linearity measurements, the DAC was programmed to output all 256 codes, creating a DC ramp in steps at the output.…”