This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Yfunction method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.
Operating Si quantum dot (QD) arrays requires homogeneous and ultra-dense structures with aggressive gate pitch. Such a density is necessary to separately control the QDs chemical potential (i.e. charge occupation of each QD) from the exchange interaction (i.e. tunnel barriers between each QD). We present here a novel Si quantum device integration that halves the effective gate pitch and provides full controllability in 1D FDSOI QD arrays. The major advantages of this architecture are explored through numerical simulations. Functionality of the fabricated structure is validated via 300K statistical electrical characterization, while tunnel-coupling control is demonstrated at cryogenic temperature.
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