TCAD simulations of FDSOI devices down to deep cryogenic temperature

Catapano, E.; Cassé, M.; Gaillard, F.; Franceschi, S. De; Meunier, Tristan; Vinet, M.; Ghibaudo, G.

doi:10.1016/j.sse.2022.108319

Cited by 10 publications

(11 citation statements)

References 10 publications

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“…The baseline FDSOI device, as shown in figure 1, is simulated using the Sentaurus TCAD tool [44]. A drift-diffusion model is considered for carrier transport, consistent with the existing literature, including for devices of smaller channel lengths [46][47][48][49][50][51]. Due to having variation in between source/drain channel doping in the lateral direction, which impacts the bandgap at the junctions, a bandgap narrowing effect is included in the simulations.…”

Section: Simulations and Benchmarking Of Baseline Fdsoi Devicementioning

confidence: 99%

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Kansal,

Medury

2024

Semicond. Sci. Technol.

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Dielectrically modulated (DM) Negative Capacitance Field Effect Transistor (NCFET) based label-free Biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nano-cavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-sided spacer region as a nano-cavity, in a Fully Depleted Silicon-on-insulator (FDSOI) based NCFET architecture. The Ferroelectric (FE) layer in the Metal-Ferroelectric-Insulator-Semiconductor (MFIS) configuration meaningfully alters the impact of drain's electric field on the source-sided electrostatics, which results in higher sensitivity. Having quantified the sensitivity for an FE-DE gate stack based NCFET Biosensor, we now propose to include a Paraelectric (PE) layer between Ferroelectric (FE) and Dielectric (DE) materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both the stacks, where a remarkable improvement is seen in the FE-PE-DE gate stack based NCFET with nearly identical linearity performance as seen from the high value of Pearson's coefficient (r2 ≥ 0.9). Therefore, in order to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), dielectric constant (kBio) values in the range of kBio = 4.5 to kBio = 75.99 are considered. Finally, the effect of scaling the channel length (Lg) on the sensitivity of the FE-PE-DE NCFET device is shown and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET Biosensor.

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Section: Simulations and Benchmarking Of Baseline Fdsoi Devicementioning

confidence: 99%

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Kansal,

Medury

2024

Semicond. Sci. Technol.

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“…The local electrical conductivity 𝜎 in the silicon channel is evaluated by considering a standard mobility law both depending on temperature, local vertical electric field 𝐹 𝑦 and lateral electric field 𝐹 𝑥 as [11,17,19],…”

Section: Electro-thermal Transport Equationsmentioning

confidence: 99%

“…The electron density n is evaluated through an analytical approximation of the Fermi-Dirac function valid from Boltzmann to metallic statistics and given by [11,17],…”

Section: Electro-thermal Transport Equationsmentioning

confidence: 99%

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

G. Ghibaudo,

M. Cassé,

F. Balestra

2023

WJP

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Self-heating (SHE) TCAD numerical simulations have been performed, for the first time, on 30nm FDSOI MOS transistors at extremely low temperatures. The self-heating temperature rise 𝑑𝑇 𝑚𝑎𝑥 and the thermal resistance 𝑅 𝑡 ℎ are computed as functions of the ambient temperature 𝑇 𝑎 and the dissipated electrical power (𝑃 𝑑 ), considering calibrated silicon and oxide thermal conductivities. The characteristics of the SHE temperature rise 𝑑𝑇 𝑚𝑎𝑥 (𝑃 𝑑 ) display sub-linear behavior at sufficiently high levels of dissipated power, in line with standard FDSOI SHE experimental data. It has been observed that the SHE temperature rise 𝑑𝑇 𝑚𝑎𝑥 can significantly exceed the ambient temperature more easily at very low temperatures. Furthermore, a detailed thermal analysis of the primary heat flows in the FDSOI device has been conducted, leading to the development of an analytical SHE model calibrated against TCAD simulation data. This SHE analytical model accurately describes the 𝑑𝑇 𝑚𝑎𝑥 (𝑃 𝑑 ) and 𝑅 𝑡 ℎ (𝑇 𝑎 ) characteristics of an FDSOI MOS device operating at extreme low ambient temperatures. These TCAD simulations and analytical models hold great promise for predicting the SHE and electro-thermal performance of FDSOI MOS transistors against ambient temperature and dissipated power.

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“…In this study, we used the semiconductor simulation software Sentaurus TCAD to design and investigate the performance of β-Ga 2 O 3 MOSFET power devices. By altering the relevant parameters of the device, we obtained the optimal parameters for device performance design [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Design of lateral β-Ga₂O₃ MOSFET with PFOM of 769.42 MW cm^–2

Zhang,

Luan

2024

Eng. Res. Express

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The Power Figure of Merit (PFOM = Vbr2/Ron,sp) is used to evaluate the performance of Gallium Oxide (β-Ga2O3) power devices. In this study, a lateral β-Ga2O3 MOSFET device is designed. The effects of different gate lengths, gate-drain distances, and epitaxial layer doping concentrations on the device performance are investigated. It is found that when the gate length is 3μm, the breakdown voltage of the device is 3099V, which is approximately twice that of devices with other gate lengths. The PFOM of the device reaches 769.14 MW/cm2. Furthermore, the breakdown voltage exhibits a trend of initially decreasing and then increasing with the increase of the gate-drain distance. When the gate-drain distance is 37μm, the breakdown voltage of the device reaches 4367V. Additionally, it is observed that the device performance is optimal when the epitaxial layer doping concentration is 2×1017cm-3. This study provides a new approach for the design of Gallium Oxide power devices.

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TCAD simulations of FDSOI devices down to deep cryogenic temperature

Cited by 10 publications

References 10 publications

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

Design of lateral β-Ga₂O₃ MOSFET with PFOM of 769.42 MW cm^–2

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TCAD simulations of FDSOI devices down to deep cryogenic temperature

Cited by 10 publications

References 10 publications

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

Design of lateral β-Ga2O3 MOSFET with PFOM of 769.42 MW cm–2

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Design of lateral β-Ga₂O₃ MOSFET with PFOM of 769.42 MW cm^–2