On the Zero Temperature Coefficient in Cryogenic FD-SOI MOSFETs

Catapano, E.; Frutuoso, T. Mota; Cassé, M.; Ghibaudo, G.

doi:10.1109/ted.2022.3215097

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…( 2b)). The presence of a zero-temperature-coefficient point is also noticeable and well in line with experimental results [2,20,26]. One should also note the strong decrease with ambient temperature of the subthreshold swing SS (= 𝑑𝑉 𝑔1 /dlog(I 𝑑 )) associated to the thermal energy reduction.…”

Section: Resultssupporting

confidence: 87%

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

G. Ghibaudo,

M. Cassé,

F. Balestra

2023

WJP

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Self-heating (SHE) TCAD numerical simulations have been performed, for the first time, on 30nm FDSOI MOS transistors at extremely low temperatures. The self-heating temperature rise 𝑑𝑇 𝑚𝑎𝑥 and the thermal resistance 𝑅 𝑡 ℎ are computed as functions of the ambient temperature 𝑇 𝑎 and the dissipated electrical power (𝑃 𝑑 ), considering calibrated silicon and oxide thermal conductivities. The characteristics of the SHE temperature rise 𝑑𝑇 𝑚𝑎𝑥 (𝑃 𝑑 ) display sub-linear behavior at sufficiently high levels of dissipated power, in line with standard FDSOI SHE experimental data. It has been observed that the SHE temperature rise 𝑑𝑇 𝑚𝑎𝑥 can significantly exceed the ambient temperature more easily at very low temperatures. Furthermore, a detailed thermal analysis of the primary heat flows in the FDSOI device has been conducted, leading to the development of an analytical SHE model calibrated against TCAD simulation data. This SHE analytical model accurately describes the 𝑑𝑇 𝑚𝑎𝑥 (𝑃 𝑑 ) and 𝑅 𝑡 ℎ (𝑇 𝑎 ) characteristics of an FDSOI MOS device operating at extreme low ambient temperatures. These TCAD simulations and analytical models hold great promise for predicting the SHE and electro-thermal performance of FDSOI MOS transistors against ambient temperature and dissipated power.

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Section: Resultssupporting

confidence: 87%

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

G. Ghibaudo,

M. Cassé,

F. Balestra

2023

WJP

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“…We notice that this ZTC point occurs around V GS =0.6V for NMOS GO1 and GO2, and above |V GS |=1V for PMOS GO1 and GO2, and slightly varies with V DS and the transistor geometry (W and L). This ZTC point results from the temperature behavior of the Fermi-Dirac function, which controls the subband carrier population (10), and is not due to a compensation effect between carrier mobility and threshold voltage temperature variation as sometimes stated. This ZTC point is responsible in particular of the low I ON improvement at |V GS |=0.9V for GO1 devices shown in Fig.…”

Section: Box Boxmentioning

confidence: 79%

(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI

Cassé¹,

Paz²,

Bergamaschi³

et al. 2023

ECS Trans.

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We present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as low as 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed. We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling.

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“…In addition, when the gate-source voltage V gs is about À4.6 V, the output current is almost unaffected by the temperature at the same drainsource voltage V ds , yielding a zero-temperature coefficient (ZTC) characteristic, which is due to the temperature dependence of the device's electrical parameters contributing in the opposite way. [58][59][60] As the temperature increases, the V off shifts to a more negative value because of the effect of the donor-like trap, causing the current to increase for the same V gs . [32] Besides, the increase in temperature causes the degradation of electron mobility, resulting in a decrease in current.…”

Section: Model Verification and Analysismentioning

confidence: 99%

An Extended Temperature Model Based on the Trapping Effect for Drain‐Source Current in GaN HEMTs

Wu,

Yao,

Liu

et al. 2024

Physica Status Solidi (a)

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In this work, an extended temperature current–voltage (I–V) model for AlGaN/GaN high electron mobility transistors (HEMTs) is proposed. Since there is no carrier freeze‐out effect in GaN HEMTs, the current density, switching characteristics, and heat dissipation performance are significantly improved with the decrease in temperature. The threshold voltage drift phenomenon can be accurately described at various temperatures by the trapping effect control potential model. Based on Matthiessen's law, the applicable temperature range of the mobility model is further extended. At cryogenic temperatures, the saturation current, saturation velocity, and sub‐threshold swing of the device tend to saturate as well as be temperature‐independent, which can be accurately modeled by using the equivalent temperature and applying the crucial temperature to quantify the turning point. Furthermore, the SHE modeling incorporates the temperature dependence of the material's thermal conductivity. The accuracy of the model is verified by experimental data at low (4.2–300 K) and high (298–773 K) temperatures. The proposed model overcomes the limitations of existing models applied at wide ambient temperatures.

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On the Zero Temperature Coefficient in Cryogenic FD-SOI MOSFETs

Cited by 9 publications

References 13 publications

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

Numerical simulation and analytical modelling of self-heating in FDSOI MOSFETs down to very deep cryogenic temperatures

(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI

An Extended Temperature Model Based on the Trapping Effect for Drain‐Source Current in GaN HEMTs

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