Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS

Abstract

Analog and RF mixed-signal cryogenic-CMOS circuits with ultra-high gain-bandwidth product can address a range of applications such as interface circuits between Superconducting Single-flux Quantum (SFQ) logic and cryo-DRAM memory, circuits for sensing and controlling qubits faster than their de-coherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18nm gate length (LG) FDSOI NMOS and PMOS from 300K to 5.5K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency (fT) of 495/337 GHz (1.35x /1.25x gain over 300K) and peak maximum oscillation frequency (fMAX) of 497/372 GHz (1.3x gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperatureinvariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.

Cryogenic Storage Memory with High‐Speed, Low‐Power, and Long‐Retention Performance

“…I D -V G curve 22 nm FDSOI MOSFET at 300 K (red) and 70 K (blue) for peripheral circuit modeling. [2] energy saving is 81%, 88%, and 87% for read, ERS, and PGM, respectively. Without the heat loss via the cable being considered, energy consumption of the SONS memory is slightly larger than that of the SONOS memory owing to the cooling power even though it is still advantageous in terms of latency.…”

“…For the peripheral circuits modeling, models of a 22 nm Q8: fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (FDSOI MOSFET) at 300 and 77 K (Figure 9) were used. [2] By updating the technology library with the cryogenic model, DESTINY, [12] a variant of NVSim [13] (the memory system-level simulation framework) was used to estimate energy and power consumption for an interface between a host processor and an SSD. To determine the number of cables and their physical parameters such as thermal conductivity and diameter, the Intel the open NAND flash interface (ONFI) 5.0 interface protocol and commercial coaxial cable data (Lake Shore Cryotronics) were referred in this simulation.…”

“…For the peripheral circuits modeling, models of a 22 nm Q8: fully‐depleted silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect‐transistor (FDSOI MOSFET) at 300 and 77 K ( Figure ) were used. [ 2 ]…”

“…This enables various attractive applications including high performance cloud-computing, space electronics, and quantum computing. [1] While semiconductor chips are manufactured based on logic transistors and memory devices, previous studies have solely focused on the logic part [2] and dynamic random-access memory [3] in cryogenic conditions. However, as the next level in the memory hierarchy, the flash storage memory has been largely unexplored at low temperature.…”

Cryogenic CMOS RF Device Modeling for Scalable Quantum Computer Design

“…To address such challenges, previous work [12] studied several on-chip microwave passive components at 4.2 K. Furthermore, [13] and [14] attempted to develop the small-signal equivalent circuit model of the FD-SOI devices at cryogenic temperatures, yet the transconductance and equivalent RC components were directly derived from the experimental values (i.e., which varied from device to device). Alternatively, a more general approach to build a cryo-CMOS RF compact model is by augmenting the intrinsic device compact model with external sub-circuit parasitic components [17].…”