Investigation of long channel bulk MOSFETs threshold voltage model down to 10 mK and key analog parameters at 4 K

Abstract

Threshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) and gm/IDS related parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.