Efficient multi-V<inf>T</inf> FDSOI technology with UTBOX for low power circuit design

Abstract

For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve ION current improvement by 45% for LVT options at an IOFF current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um 2 bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔVT versus Vb ~ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances. IntroductionThin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the CET and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical threshold voltage (VT~0.45V) for both NMOS and PMOS devices [1], still one major challenge is to provide Multi-VT devices and dynamic VT modulation with an undoped channel in order to satisfy the low power (LP) circuit design requirements [2][3][4]. To overcome this issue, a simple and novel Multi-VT strategy has been proposed in [2], combining UTBOX substrate with different back plane (BP) and back biasing (Vb). This method based on single metal gate for process simplicity and cost saving is also very attractive thanks to the possibility to re-use the bulk forward (FBB)/reverse (RBB) biasing techniques. In this paper, the viability of this concept is demonstrated through silicon results across wafers in 45nm technology. Firstly, the electrical characteristics of the high-(HVT) standard-(SVT) and Low-(LVT) VT devices options are presented. Second, the RBB and FBB back biasing effectiveness for the static power and dynamic performance management is demonstrated on ring oscillators (RO) and 0.299µm 2 6T SRAM bitcells. Device fabrication and Multi-V T familiesThe FDSOI devices were processed on 300mm (100) UNIBOND TM SOI wafers with a buried oxide thickness of 10nm via the process flow scheme presented in Fig.2. The final silicon film thickness under the gate is 8nm, the nominal gate length is 40nm and the EOT 14Å (Fig.1). The use of UTBOX leads to further SCE improvement but has to be combined with a BP in order to suppress the depleted zone created under the BOX [5]. Fig.3 shows the three NMOS device VT configurations implemented in this study. For NMOS, the HVT and LVT options are based on a p-type BP set to 0V and ntype BP set to Vdd, respectively. The SVT option does not include BP and the back bias (Vb) is set to 0V. For the PMOS device, complementary BP doping type and biasing are applied [2]. All of these devices can be simply co-integrated in a circuit thanks to their configuration which avoids forward PN junctions in the substrate. The table in Fig.4a shows the electrical cha...

Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes

“…The second degree of freedom is the !ength of the transistors. Un!ike the width, ап increase in !ength induces а decrease of ld,peak because of Y; h roll-off in this techno!ogy [7] while improving the Id,peak/1d,valley ratio thanks to а steeper sub thresho!d s!ope. The !ast parameter is the back-bias vo!tage.…”

“…The !ast parameter is the back-bias vo!tage. А high forward back-bias (FBB) allows to dramatically enhance the peak current Ьу reducing Y; h [7] whi!e preserving more or less the ratio Id,peak/1d,valley. Notice that FBB сап not take апу уа!ие for two reasons: FBB must Ье generated on-chip and FBB will Ье used to compensate the corner variations.…”

Ultra-thin films and multigate devices architectures for future CMOS scaling

“…Thus, the thicker the buried oxide, the higher the source to drain coupling will be. Scaling down of the buried oxide is mandatory to maintain the electrostatic characteristics of MOSFETs (Figure 6(a)) [25][26][27][28]. Recent results have shown that [29,30]; (b) strained dual channel CMOS process flow [29].…”

“…buried oxide could be scaled to 10 nm on large 300 mm diameter wafers with Si layers as thin as 6 nm [25][26][27][28]. The control of such substrates could lead to multi-threshold control.…”

“…The control of such substrates could lead to multi-threshold control. This could allow for large scale integration for state-of-the-art systems-on-a-chip (SOC) [25,26]. A very important figure of merit that emphasizes SOI advantages over bulk technology is shown in Figure 6(b) [27]; for a given propagation delay time, ring oscillators demonstrate lower dynamic powers, P dyn , than bulk technology.…”