Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes

Abstract

Ultra-Iow-power (ULP) diodes are special 2-Т struc tures f'eaturing а unique negative-diff'erential resistance charac teristic that сап Ье used to build а 4-Т ULP latch for f1ip-flop or SRAM applications. In tbls paper, we explore the area/mismatch tradeoff' in such а ULP latch for ultra-Iow-voltage (ULV) SoCs in 28 пm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6а robustness of the latch against mismatch while maintaining а leakage power below 10 pW. Under these constraints, the use of' а genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both f1ip-flop and SRAM applications.lndex Terтs-CMOS integrated circuits, diode, latch, low leakage, low power, low voltage, memory, SRAM, f1ip-flop.