Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

Coquand, R.; Cassé, M.; Barraud, S.; Leroux, Paul; Cooper, David; Vizioz, C.; Comboroure, C.; Perreau, P.; Maffini-Alvaro, V.; Tabone, C.; Tosti, L.; Allain, F.; Barnola, S.; Delaye, V.; Aussenac, F.; Reimbold, G.; Ghibaudo, G.; Munteanu, Daniéla; Monfray, S.; Bœuf, F.; Faynot, O.; Poiroux, T.

doi:10.1109/vlsit.2012.6242437

Cited by 24 publications

(19 citation statements)

References 5 publications

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“…Mobility measurements on n-and p-type SOI and sSOI transistors were performed on arrays of 50 NWs in parallel by using the conventional CV-split method [7]. Figs.…”

Section: Resultsmentioning

confidence: 99%

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Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Barraud¹,

Laviéville²,

Tabone³

et al. 2014

2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

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High-performance strainedSilicon-OnInsulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with I ON current of 1410 μA/μm (when I OFF = 70 nA/μm) at V DD =0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SS SAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an I ON improvement up to +40% at short gate lengths. More generally, size-and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.

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“…Mobility measurements on n-and p-type SOI and sSOI transistors were performed on arrays of 50 NWs in parallel by using the conventional CV-split method [7]. Figs.…”

Section: Resultsmentioning

confidence: 99%

“…This can be explained by the sidewalls contribution. The (110) sidewalls have a beneficial crystallographic orientation for hole transport, whereas μ e is weakened with respect to (100) top-surface [7]. The stronger quantum confinement in NWs also contributes to increase the electron-phonon coupling and reduce μ e .…”

Section: Resultsmentioning

confidence: 99%

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Barraud¹,

Laviéville²,

Tabone³

et al. 2014

2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

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“…We fabricated NWs with high-κ/metal gate stack on 300 mm (100) SOI and sSOI wafers with 145 nm BOX, resulting from technological steps described in [5,6]. The (s)Si thickness (NW height H NW ) is 11 nm.…”

Section: Device Fabricationmentioning

confidence: 99%

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of I<inf>DS</inf> and mobility oscillations

Coquand

Barraud

Cassé

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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This paper describes low-field electron transport in nanowire FETs with high-κ/metal gate fabricated on 300 mm SOI and strained-SOI substrates. We studied the temperature and size dependences of gatechannel capacitance (C GC ) and effective mobility (µ EFF ) down to 8 nm width. We show that the electron mobility is strongly reduced for sub-10 nm widths. Low-temperature measurements show a quantum oscillatory behavior of mobility revealing the electron confinement in 1D subbands structure of nanowires for temperature below 50K.

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“…It also allows an efficient strain engineering of the channel and Source/Drain to boost the transistor performance. Particularly, it is possible to replace standard unstrained SOI substrates (SOI) by strained SOI substrates (sSOI) to improve the drive current and adjust the V th of NMOSFETs [1,2]. However the effect of this performance booster on the intrinsic reliability of the transistor has not been extensively studied so far.…”

Section: Introductionmentioning

confidence: 99%

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

Besnard¹,

Garros²,

Subirats³

et al. 2015

2015 IEEE International Reliability Physics Symposium

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In this paper, we investigate the potential of strained Silicon-On-Insulator (sSOI) for the future advanced CMOS nodes. Strained FDSOI depicts a 30% higher performance in term of I ON /I OFF thanks to higher mobility. Changes in band structure reduce the gate leakage and devices depict superior HC reliability at same drive current. The better interface quality with sSi layer leads to higher immunity to dangling bonds generation. Strain integration does not affect BTI and breakdown reliability.

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Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

Cited by 24 publications

References 5 publications

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of I<inf>DS</inf> and mobility oscillations

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

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