A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

DeSalvo, B.; Morin, P.; Pala, Marco G.; Ghibaudo, G.; Rozeau, O.; Liu, Q.; Pofelski, Alexandre; Martini, S.; Cassé, M.; Pilorget, S.; Allibert, F.; Chafik, F.; Poiroux, T.; Scheer, P.; Southwick, Richard G.; Chanemougame, D.; Grenouillet, L.; Cheng, K.; Andrieu, F.; Barraud, S.; Maitrejean, S.; Augendre, E.; Kothari, H.; Loubet, N.; Kleemeier, W.; Celik, M.; Faynot, O.; Vinet, M.; Sampson, R.; Doris, B.

doi:10.1109/iedm.2014.7047002

Cited by 20 publications

(11 citation statements)

References 15 publications

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“…2 In Silicon Germanium alloys, it has been shown that tensile strain is detrimental to hole mobility in this strain range. 3 This means that, cSiGe pFET on strained SOI wafer result in a loss of the hole mobility gain and consequently device performance are reduced compared to the equivalent devices on SOI wafer.…”

Section: Fd-soi Devices Process and Resultsmentioning

confidence: 99%

“…Each point is the average over nearly 20 measurements on the wafer, the standard deviation falling in the symbol size. Simulated electron mobilities [3] for various tensile strains correspond to dotted lines.…”

Section: Fd-soi Devices Process and Resultsmentioning

confidence: 99%

“…Recent results have shown record performance value for FD-SOI nFET. 2 Moreover, using multi-scale modelling, De Salvo et al 3 demonstrate that mobility enhancement can also be a powerful tool for power management in FD-SOI technology.…”

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confidence: 99%

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Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

Maitrejean¹,

Loubet

Augendre³

et al. 2015

ECS J. Solid State Sci. Technol.

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Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si 1-x Ge x on SOI substrate, the partial amorphization and crystallization of the Si/Si 1-x Ge x bilayers and the selective removal of the top Si 1-x Ge x film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted-SOI (CMOS FD-SOI) devices, with gate length lower than 15 nm, were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.

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Section: Fd-soi Devices Process and Resultsmentioning

confidence: 99%

Section: Fd-soi Devices Process and Resultsmentioning

confidence: 99%

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Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

Maitrejean¹,

Loubet

Augendre³

et al. 2015

ECS J. Solid State Sci. Technol.

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“…When combined with uni-axially strained raised SiGe source/drain, it requires a rigorous 3D mechanical simulation methodology to obtain realistic and layout dependent simulations [8], [9]. As illustrated Fig.…”

Section: B Modeling Of Strainmentioning

confidence: 99%

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

Tavernier

Pereira

Nier

et al. 2015

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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This paper reviews the main challenges for the TCAD of 14nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology performance assessment. Thanks to a multi-scale approach combining extensive electrical characterization and advanced solvers simulations, ensuring deep physical insight, we provide TCAD simulation framework for device layout optimization, strain engineering and device reliability assessment.

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“…The use of mobility boosters is an effective way to improve CMOS performance and reduce power consumption [1][2][3][4][5][6]. Hole mobility is higher for pMOSFETs using compressive Si or compressive SiGe channels [2][3][4][5][6] whereas electron mobility is higher for nMOSFETs using tensile Si [3,5,6].…”

Section: Introductionmentioning

confidence: 99%

New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

Bonnevialle

Reboh

Grenouillet

et al. 2015

EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

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We demonstrate the fabrication of strained Si-OnInsulator (sSOI) using a relaxation process of a compressive SiGe layer on SOI, and the transfer of lattice parameter from the relaxed SiGe to the Si layer. This process is based on a partial amorphization and recrystallization of the SiGe/Si stack. We used HRXRD (High Resolution X-Ray Diffraction) and TEM (Transmission Electron Microscopy) to characterize the microstructure of the layers. Strain and Stress evolutions throughout the process were determined using Raman spectroscopy and wafer bow measurements. Using a stack of 40 nm Si 0.7 Ge 0.3 on 9 nm Si, we obtained tensile Si layer having a stress of + 1.6 GPa which corresponds to a 80% lattice parameter transfer from SiGe to Si.

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A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

Cited by 20 publications

References 15 publications

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

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