Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGex on SOI substrate, the partial amorphization and crystallization of the Si / Si1-xGex bilayers and the selective removal of the top Si1-xGex film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted- SOI (CMOS FD-SOI) devices at 14 nm node design rules were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.
Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si 1-x Ge x on SOI substrate, the partial amorphization and crystallization of the Si/Si 1-x Ge x bilayers and the selective removal of the top Si 1-x Ge x film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted-SOI (CMOS FD-SOI) devices, with gate length lower than 15 nm, were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.
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