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Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90nm SRAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array.A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling.

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A novel programmable element has been developed and evaluated for state of the art CMOS processes. This element is based on agglomeration of the Ti-silicide layer on top of poly fuses. Various aspects of this programmable device including characterization and optimization of physical and electrical aspects of the element, programming yield, and reliability have been studied. Development of a novel programming and sensing circuit is also included.step. Typically, a fuse link is drawn at minimum allowable width with a few microns of length (see Fig. 2). IntroductionThe capability of implementing a small PROM array or logic products at no additional process cost is high11 desirable for a number of applications such as redundancy Fig. 1, Cross section of the damaged section of a programmed fuse. Lack of implementation in SRAMs, die identification, electrically COllaterd damage to the overlying and underlying layers 1s evident.. programmable feature selection, etc.As CMOS technology scaled, gate oxides became thin enough that implementation of flash memory cells on standard logic CMOS processes (SPEED) became possible