BTI reliability of 45 nm high-K + metal-gate process technology

Pae, Sangwoo; Agostinelli, M.; Brazier, M.; Chau, R.; Dewey, G.; Ghani, T.; Hattendorf, M.; Hicks, J.; Kavalieros, J.; Kuhn, Kelin J.; Kühn, Markus; Maiz, J.; Metz, M.; Mistry, K.; Prasad, C.; Ramey, S.; Roskowski, A. M.; Sandford, J.; Thomas, Ciby; Thomas, J.; Wiegand, C.; Wiedemer, Jami

doi:10.1109/relphy.2008.4558911

Cited by 108 publications

(64 citation statements)

References 18 publications

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“…The differences in NBTI between HfO 2 and HfSiO x stacks can be attributed to the difference in N density in the SiO 2 IL [16], [17]. This letter shows that NBTI is strongly influenced by the IL quality, and N content in IL plays a very important role, consistent with earlier reports [8], [15], [18].…”

Section: Introductionsupporting

confidence: 89%

“…is a serious reliability concern in p-MOSFETs having Si-oxynitride (SiON) [1]- [4] and high-k [5]- [8] gate dielectrics. It is now well known that defects generated during NBT stress recovers after stress is removed, and conventional stress-measure-stress (SMS) methods suffer from recovery-related artifacts that result in incorrect degradation magnitude, time, and temperature (T ) dependence of NBTI [9], [10].…”

Section: Introductionmentioning

confidence: 99%

“…UF-OTF can be used to determine degradation from very short (approximately microseconds) to long stress time, although it requires postprocessing to convert I DLIN degradation to V T shift as discussed in [12]. However, while NBTI in SiON p-MOSFETs has been studied using UF-SMS or UF-OTF techniques [4], [11], [13], to the best of our knowledge, most studies of NBTI in high-k p-MOSFETs [5]- [8] were done using conventional SMS and calls for a reevaluation by UF methods, particularly to probe the degradation at early stress time and to have recovery-artifact-free degradation at longer stress time.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

Deora

Maheta

Bersuker

et al. 2009

IEEE Electron Device Lett.

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Abstract-The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in HfO 2 /TiN, HfSiO x /TiN, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly I DLIN technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, HfO 2 devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and HfSiO x devices. HfSiO x shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to HfO 2 , which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between HfSiO x and HfO 2 can be attributed to differences in N density in the SiO 2 IL of these devices.Index Terms-Activation energy, field acceleration, high-k dielectric, hole trapping, interface traps, negative-bias temperature instability (NBTI), plasma oxynitride, p-MOSFET, thermal oxynitride, time exponent.

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Section: Introductionsupporting

confidence: 89%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

Deora

Maheta

Bersuker

et al. 2009

IEEE Electron Device Lett.

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“…This suggests that ∆VT mostly originates in charge trapping in the oxide near the oxide/GaN interface or at the interface itself in interface states. Both are known to affect the mobility [17,22]. For long stress times, trapping further away from the interface eventually takes place producing an additional VT shift without a corresponding decrease in gm,max.…”

Section: A Mechanisms Responsible For Vt Shift Under Pbtimentioning

confidence: 99%

“…This indicates permanent mobility degradation. Studies have attributed this to the generation of oxide traps close to the oxide/semiconductor interface [17,22].…”

Section: B Modelmentioning

confidence: 99%

Positive-bias temperature instability (PBTI) of GaN MOSFETs

Alamo

2015

2015 IEEE International Reliability Physics Symposium

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-We have investigated the stability of the gate stack of GaN n-MOSFETs under positive gate stress. Devices with a gate dielectric that consists of pure SiO2 or a composite SiO2/Al2O3 bilayer were studied. Our research has targeted the evolution of threshold voltage (VT), subthreshold swing (S) and transconductance (gm) after positive gate voltage stress of different duration at different voltages and temperatures. We have also examined the recovery process after the stress is removed. We have observed positive VT shift (∆VT) in both gate dielectrics under positive gate stress. In devices with a SiO2 gate oxide, we have found that ∆VT is caused by a combination of electron trapping in pre-existing oxide traps and interface trap generation. In devices with a composite SiO2/Al2O3 gate oxide, on the other hand, ∆VT is due to electron trapping in pre-existing oxide traps and generation of near interface oxide traps.

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Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics

Wong¹

2010

Integrated Circuits and Systems

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BTI reliability of 45 nm high-K + metal-gate process technology

Cited by 108 publications

References 18 publications

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

Positive-bias temperature instability (PBTI) of GaN MOSFETs

Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics

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