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Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90nm SRAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array.A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling.

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The size of the advanced Cu interconnects has been significantly reduced, reaching the current 7.0 nm node technology and below. With the relentless scaling-down of microelectronic devices, the advanced Cu interconnects thus requires an ultrathin and reliable diffusion barrier layer to prevent Cu diffusion into the surrounding dielectric. In this paper, amorphous carbon (a-C) layers of 0.75–2.5 nm thickness have been studied for use as copper diffusion barriers. The barrier performance and thermal stability of the a-C layers were evaluated by annealing Cu/SiO2/Si metal-oxide-semiconductor (MOS) samples with and without an a-C diffusion barrier at 400 °C for 10 h. Microstructure and elemental analysis performed by transmission electron microscopy (TEM) and secondary ion mass spectroscopy showed that no Cu diffusion into the SiO2 layer occurred in the presence of the a-C barrier layer. However, current density-electric field and capacitance–voltage measurements showed that 0.75 and 2.5 nm thick a-C barriers behave differently because of different microstructures being formed in each thickness after annealing. The presence of the 0.75 nm thick a-C barrier layer considerably improved the reliability of the fabricated MOS samples. In contrast, the reliability of MOS samples with a 2.5 nm thick a-C barrier was degraded by sp2 clustering and microstructural change from amorphous phase to nanocrystalline state during annealing. These results were confirmed by Raman spectroscopy, X-ray photoelectron spectroscopy and TEM analysis. This study provides evidence that an 0.75 nm thick a-C layer is a reliable diffusion barrier.

PURPOSE PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated [I J, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.PMOS NBTI transistor degradation is an important reliability mechanism and has been shown to be one of the major limiters for product lifetime [2,3].PMOS N3TI effects originate from the formation of fixed oxide charge and the creation of interface states. These effects manifest themselves as shifts in threshold voltage and transconductance, For large gate area devices, these shifts can cause failure of digital circuits to meet timing windows or can create undesirable mismatch in analog circuits.Recent observations on PMOS devices with small gate areas show that the degradation of both drain current and threshold voltage appear to be subject to random fluctuations.These fluctuations increase a5 a function of stress time and are affected by the current density. It is believed that the additional instability is due a discrete random trapped charge effect, similar to what has been recently observed for discrete-trap memories [4]. The trapped charge can occur at random locations across the gate and can affect the drain current de-pending on the local current density. This paper examines the effects of PMOS NBTI-induced random fluctuations on device degradation. It clearly demonstrates that this geometric effect is due to the statistical nature of random trapped charge in the oxide and the effect of this charge on the percolation path through the channel of a small gate area device. MODELINGThe statistical nature of the random charge effect can be modeled in a similar fashion as has been done for random dopants. Charges placed at discrete points in the channel region can constrict the current flow in a small gate area devices by locally modifylng the threshold voltage. As illustrated in Figure 1, if random charges are placed at discrete points along a conducting path from source to drain, the current flow will be forced to areas of lower threshold voltage and could possibly be shut off entirely. CHANKEL FIGURE 1: ILLUSTRATION OF CURRENT FLOW FROM SOURCE TO DRAW IN A SMALL GATE AREA DEVICE. OPEN CIRCLE REPRESENT FILLED TRAPS THAT ALTER THE CURRENT FLOW FROM SOURCE TO DRAIN. Keyes [5] derived a relationship expressing the fluctuation in the threshold voltage as a function of channel doping and gate area. In this derivation, the probability of a conducting path from source to drain is determined by the local probability of a given area in the channel having a number of impurities less than a critical threshold, m,. This probability can be...