1Gbit High Density Embedded STT-MRAM in 28nm FDSOI Technology

Lee, K.; Kim, W. J.; Lee, J. H.; Bae, Byoung-Jae; Park, J. H.; Kim, I. H.; Seo, Bong-Gun; Han, Shin-Hee; Ji, Yongsung; Jung, Hoeryong; Park, S. O.; Bak, Jung Hoon; Kwon, Oh-Hyun; Kye, Jongwook; Kim, Y. D.; Pae, Sangwoo; Song, Yoo Sung; Jeong, Gitae; Hwang, Kyusung; Koh, G.H.; Kang, Ho-Kyu; Jung, Eui S.; Kim, Y. J.; Kim, C. K.; Antonyan, Artur; Chang, Donghoon; Hwang, Seongtaek; Lee, G. W.; Ji, Nan

doi:10.1109/iedm19573.2019.8993551

Cited by 66 publications

(27 citation statements)

References 6 publications

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“…The tunability of these aspects makes it customizable as both embedded and discrete memory solutions for a variety of applications such as Internet-of-Things (IoT), automotive, aerospace, and last-level caches [2]. Therefore, STT-MRAM technology has received a large amount of attention for commercialization from major semiconductor companies such as TSMC [2], Samsung [3], Intel [4], and SK hynix [5]. To enable STT-MRAM mass production, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers.…”

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confidence: 99%

“…To enable STT-MRAM mass production, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers. The STT-MRAM manufacturing process involves not only conventional CMOS process but also MTJ fabrication and integration [3]. The latter is more vulnerable to defects as it requires deposition, etch, and integration of magnetic materials with new tools [6].…”

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confidence: 99%

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Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Rao

Taouil

et al. 2020

2020 IEEE International Test Conference (ITC)

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Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in both the hard layer and reference layer of MTJ devices undergoes an unintended flip to the opposite direction. Both magnetic and electrical measurement data of SAFF defect in fabricated MTJ devices is presented; it shows that such a defect reverses the polarity of stray field at the free layer of MTJ, while it has no electrical impact on the single isolated device. The paper also demonstrates that using the conventional fault modeling and test approach fails to appropriately model and test such a defect. Therefore device-aware fault modeling and test approach is used. It first physically models the defect and incorporate it into a Verilog-A MTJ compact model, which is afterwards calibrated with silicon data. The model is thereafter used for fault analysis and modeling within an STT-MRAM array; simulation results show that a SAFF defect may lead to a transient passive neighborhood pattern sensitive fault (tPNPSF) when all neighboring cells are in logic '1' state. Finally, test solutions for such fault are discussed.Index Terms-Device-aware test, STT-MRAMs, manufacturing defects, fault models• Discover a new STT-MRAM-specific defect based on silicon measurements; the defect is referred to as SAFF. • Present magnetic and electrical characterization of MTJ devices with the SAFF defect.

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confidence: 99%

mentioning

confidence: 99%

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Rao

Taouil

et al. 2020

2020 IEEE International Test Conference (ITC)

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“…Subsequently, leading semiconductor industries and tool suppliers have aggressively launched their development programs for STT-MRAM in terms of either eFlash or SRAM replacement. For example, Intel announced NOR-Flash replacement, while Samsung and Everspin/GF announced the release of a 1 Gb STT-MRAM on the 28 nm node [31]. Besides STT-MRAM, RRAM, and PCM operate based on the rearrangement of atomic configurations and hence have worse access times (write speed) and cycling endurance than MRAM.…”

Section: Emerging Nonvolatile Memory: Devices and Chipsmentioning

confidence: 99%

Recent progress of integrated circuits and optoelectronic chips

Xiang

Han

Zhang

et al. 2021

Sci. China Inf. Sci.

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Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called "Moore's law" in the past 60 years, and now has entered the post Moore's law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.

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“…[94] (of approximately 1 µA/MHz/b). Embedded STT-MRAMs with a capacity of up to 1 Gb were fabricated for industrial MCU/IoT applications based on a 28-nm FDSOI process, and endurance of 10 10 was reported [95][96][97]. The planer FDSOI CMOS process provides tunable energy efficiency, e.g., forward/reverse body biasing, thereby alleviating the previous in-MRAM computational limitations.…”

Section: Energy Efficiency Challengementioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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1Gbit High Density Embedded STT-MRAM in 28nm FDSOI Technology

Cited by 66 publications

References 6 publications

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Recent progress of integrated circuits and optoelectronic chips

A survey of in-spin transfer torque MRAM computing

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