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A two-dimensional analytical model for LACGAS SGT has been developed, and its impact on the device characteristics has been discussed. It has been demonstrated that the incorporation of LACGAS design ensures better screening from drain bias variations leading to a reduction in DIBL. The effectiveness of LACGAS design can also be seen as a delayed onset of V th rolloff with decreasing channel lengths and a reduction in the subthreshold slope. Furthermore, the peak in the electric field distribution under the gate is higher for LACGAS when compared with UD devices, which ensures uniformity in the average drift velocity of the electrons in the channel and this leads to an improvement in the carrier transport efficiency. It was also observed that LACGAS design leads to a reduction in the peak electric field near the drain end when compared with UD devices, which can be interpreted as a reduction in impact ionization and hot-carrier effects. Furthermore, LACGAS SGT is found to have higher drain current and transconductance when compared with UD device. Thus, it has been demonstrated that incorporation of LAC and gate stack design leads to an improvement in short-channel immunity, hot-carrier reliability, and current drivability, while also enhancing the gate controllability and carrier transport efficiency. To gain an insight into the effectiveness of LACGAS design, the device characteristics have been compared over a wide range of parameters and bias conditions, and it is shown that LACGAS structure achieves the twin objective of miniaturization and high device performance. ACKNOWLEDGMENTSThe authors are grateful to the Defense Research and Development Organization (DRDO) for providing the necessary financial assistance to carry out this work. ABSTRACT: In this article, the miniaturized resonator and bandpass filter for W-band application are suggested and evaluated on thin-film substrate. In the meanwhile, the resonator using the loading capacitor with the electrical length of 2k g /9 and the other resonator using broadside coupled line structure of k g /9 are designed and applied for the compact filter evaluation. The filter using the capacitor-loaded resonators with the dimension of 0.2 Â 0.5 mm 2 shows the insertion loss of 2.1 dB at 94 GHz, and the return loss better than 10 dB at the frequencies between 91 and 98 GHz. For the filter using broadside coupled line resonators with the size of 0.33 Â 0.24 mm 2 , the insertion loss is 2.3 dB at 92 GHz and the return loss is better than 10 dB in at the frequencies between 85 and 99 GHz. These filters show very compact dimensions retaining the filter performance commensurate with those of the filters in previous works.

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A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.