T. Ghani scite author profile

A new spin based logic device is proposed. It is comprised of a common free ferromagnetic layer separated by a tunnel junction from three inputs and one output with separate fixed layers. It has the functionality of a majority gate and is switched by spin transfer torque. Validity of its logic operation is demonstrated by micromagnetic simulation. A version of such devices with perpendicular magnetization is examined. Switching encompasses moving domain walls. The device reuses most of the materials and structures from spin torque RAM, and is entirely compatible with CMOS technology.

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T. Ghani

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

A 90-nm logic technology featuring strained-silicon

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

The High-k Solution

A Logic Nanotechnology Featuring Strained-Silicon

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

Proposal of a Spin Torque Majority Gate Logic

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T. Ghani

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

A 90-nm logic technology featuring strained-silicon

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

The High-k Solution

A Logic Nanotechnology Featuring Strained-Silicon

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &#x00B5;m<sup>2</sup> SRAM cell size

Proposal of a Spin Torque Majority Gate Logic

Contact Info

Product

Resources

About

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size