A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Mistry, K.; Allen, C.; Auth, C.; Beattie, Brian; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, Markus J.; Cappellani, A.; Chau, R.; Choi, Changhwan; Ding, G.; Fischer, K.; Ghani, T.; Grover, R.; Han, Won Seok; Hanken, Dennis G.; Hattendorf, M.; He, Jun; Hicks, J.; Huessner, R.; Ingerly, D.; Jain, Pulkit; James, R.; Jong, Lee Soo; Joshi, S.; Kenyon, C.; Kuhn, Kelin J.; Lee, K.; Liu, H.; Maiz, J.; Mclntyre, B.; Moon, Peter C.; Neirynck, J.; Pae, Sangwoo; Parker, C.; Parsons, D.; Prasad, C.; Pipes, Leonard C.; Prince, M.; Ranade, P.; Reynolds, T.E.; Sandford, J.; Shifren, L.; Sebastián, J.; Seiple, J.; Simon, Daniel K.; Sivakumar, S.; Smith, P.; Thomas, Ciby; Troeger, T.; Vandervoorn, P.; Williams, Sue; Zawadzki, K.

doi:10.1109/iedm.2007.4418914

Cited by 579 publications

(272 citation statements)

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“…The device is then covered by atomic layer deposition of 30 nm HfO 2 , a high-κ material commonly used as a gate dielectric. 30,31 Finally, local top gates are deposited in the final round of e-beam lithography and metal deposition, resulting in an integrated circuit such as the one shown in Figure 2b, composed of two single-layer transistors connected in series. The channel width of the transistors in our integrated circuit is 4.2 μm, lead spacing is 1.6 μm, and top gate length is 1.3 μm.…”

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confidence: 99%

Integrated Circuits and Logic Operations Based on Single-Layer MoS₂

2011

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Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS2 represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS2. Our integrated circuits are capable of operating as inverters, converting logical “1” into logical “0”, with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS2 transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

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Integrated Circuits and Logic Operations Based on Single-Layer MoS₂

2011

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“…1 A few hindrances exist, however, including the poor quality of the native surface oxide GeO 2 2 and the difficulty in obtaining high-enough n-type carrier concentrations for ultra-shallow junctions. 3 While the insulation issue has essentially been resolved by introducing high-j dielectrics as a replacement for SiO 2 a decade ago 4 (directly applicable to Ge), the doping limitations are still to be overcome. Hence, it is imperative to have more profound knowledge on the formation of defects and their role in the carrier compensation of Ge.…”

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confidence: 99%

Electrical compensation via vacancy–donor complexes in arsenic-implanted and laser-annealed germanium

Kalliovaara

Slotte

Makkonen

et al. 2016

Applied Physics Letters

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“…Without new inventions, MOSFET scaling and Moore's Law were threatened with the likelihood of coming to an end. Intel's 45nm logic technology was the first to introduce high-K dielectric with metal-gate transistors for improved performance and reduced leakage [8,9]. Gate-oxide equivalent oxide thickness (EOT) is scaled to 0.9nm and transistor gate pitch is scaled to 112.5nm.…”

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confidence: 99%