2014 IEEE International Electron Devices Meeting 2014
DOI: 10.1109/iedm.2014.7046976
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A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &#x00B5;m<sup>2</sup> SRAM cell size

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Cited by 342 publications
(194 citation statements)
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“…Going forward, the scope of technical challenges on this path exceeds those faced over the past decade or addressable by device-level innovation. For example, transistor leakage current and interconnect delay across a chip have continued to worsen, and commercially available transistors are close to the physical limits for subthreshold slope 40 . Leakage power has grown to become a substantial portion of total power consumption, and power consumption has limited the benefits of further scaling 41 .…”
Section: Nature Electronicsmentioning
confidence: 99%
“…Going forward, the scope of technical challenges on this path exceeds those faced over the past decade or addressable by device-level innovation. For example, transistor leakage current and interconnect delay across a chip have continued to worsen, and commercially available transistors are close to the physical limits for subthreshold slope 40 . Leakage power has grown to become a substantial portion of total power consumption, and power consumption has limited the benefits of further scaling 41 .…”
Section: Nature Electronicsmentioning
confidence: 99%
“…Advances in device size, connectivity and homogeneity are underway as well in the pursuit of scalable quantum computing, the results of which can be directly leveraged. Examples include scalable gate layouts for 1D arrays [37,38] as well as square [39] and triangular [40] geometries, industrial-grade fabrication processes [41] and magnetically quiet 28 Si substrates [42], that open up further possibilities for quantum simulation experiments with quantum dots.…”
Section: Resultsmentioning
confidence: 99%
“…The devices developped with our approach are now under systematic measurements to assess their metrological capabilities, in collaboration with NMIs. It is important to emphasize that the aggressive pitch (65 nm) we reached with our electron beam lithography gate level is now accessible with the most advanced industrial process [14] (14 nm node). …”
Section: Electrical Characterizations At 300 Kmentioning
confidence: 99%