A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Auth, C.; Allen, C.; Blattner, A.; Bergstrom, D.; Brazier, M.; Bost, M.; Buehler, Markus J.; Chikarmane, V.; Ghani, T.; Glassman, Timothy E.; Grover, R.; Han, Wu; Hanken, Dennis G.; Hattendorf, M.; Hentges, P.; Heussner, R.; Hicks, J.; Ingerly, D.; Jain, Promil; Jaloviar, S.; James, R.; Jones, D. E.; Jopling, J.; Joshi, S.; Kenyon, C.; Liu, H.; McFadden, R.S.; McIntyre, B.; Neirynck, J.; Parker, Colita; Pipes, Leonard C.; Post, Ian; Pradhan, Sambhu Nath; Prince, M.; Ramey, S.; Reynolds, T.E.; Roesler, Joachim; Sandford, J.; Seiple, J.; Smith, Peter E.; Thomas, Ciby; Towner, D. J.; Troeger, T.; Weber, C.; Yashar, P.; Zawadzki, K.; Mistry, K.

doi:10.1109/vlsit.2012.6242496

Cited by 555 publications

(256 citation statements)

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“…Hence, 3-D multigate and/or ultrathin-body devices having a lightly doped channel have been adopted in industry for sub-32-nm technology node. Despite the transistor war between FinFET/tri-gate MOSFETs [23] and FD-SOI MOSFETs [24], these advanced device structures (shown in Fig. 4) can be robust to the RDF because of the lightly doped channel and better gate-to-channel capacitive coupling of the multiple gates and/or ultra-thin bodies.…”

Section: Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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Section: Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…A three--dimensional multi--gate FinFET architecture has been adopted by Intel at the 22 nm node [1], and a fully--depleted SOI MOSFETs have been introduced by ST Microelectronics at the 28 nm node [2]. However, technology considerations and cost still render bulk planar MOSFETs an attractive technology for many markets [3].…”

Section: Introductionmentioning

confidence: 99%

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Wang

Brown

Cheng

et al. 2014

Solid-State Electronics

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Abstract-Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20--nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3--D simulation. It is found that raised drain--bias can exacerbate threshold--voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold--voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de--correlation of DIBL against threshold--voltage.

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“…However, after scaling devices down to sub-100-nm nodes, several technical challenges [e.g., intrinsic random variations and severe short-channel effects (SCEs)] emerged, some of which seemed to be insurmountable. Many non-planar MOSFETs such as FinFETs and FDSOI MOSFETs [1,2] have been suggested as an alternative for future CMOS scaling. Recently, the Segmented-channel MOSFET (SegFET) on a corrugated substrate with a quasi-planar tri-gate device structure was demonstrated [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO₂or SiO₂Trench Isolation

Nam¹,

Park²,

Shin³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of HfO 2 (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with HfO 2 , and the VSTI region is filled with SiO 2 ) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with HfO 2 , and the STI region is filled with SiO 2 ) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate (C gg ) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest C gg value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

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A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Cited by 555 publications

References 0 publications

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO₂or SiO₂Trench Isolation

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A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Cited by 555 publications

References 0 publications

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO2or SiO2Trench Isolation

Contact Info

Product

Resources

About

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO₂or SiO₂Trench Isolation