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Modular multilevel converter (MMC) has become the most promising converter technology for high voltage direct current (HVDC) transmission systems. MMC sub-module (SM) topologies with dc fault ride-through capabilities are emerging which are suitable for overhead line (OHL) applications. The hybrid SM design of each converter arm can get the compromise of higher capability of handling dc fault and lower capital investments and losses. In this paper, the initial hybrid SM numbers design method for supporting the dc-link voltage and riding-through dc faults and the optimized hybrid SM redundancy configuration strategy for effectively increasing the reliability of MMC are proposed and calculated. In contrast with previously proposed redundancy configuration for MMC with single SM topology, this approach solves the curvature of three-dimensional surface to calculate the recommended redundant hybrid SM numbers which takes both the semiconductor device utilization rate and the reliability of MMC into consideration.

Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90nm SRAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array.A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling.

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DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks.We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.

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Abstract-This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm 2 experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.Index Terms-Gigabit Ethernet, offload, packet processing, special-purpose processor, TCP.