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We examine the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18µm single-V t and 0.13µm dual-V t logic process technologies. We investigate its dependencies on channel length, target V t , temperature and technology generation. We show that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V t at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V t values are low. We present a model that relates different transistor leakage components to full-chip leakage current, and validate the model through testchip measurements across a range of RBB values.

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