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Net assignment for the FPGA-based logic emulation system in the folded-clos network structure," IEEE Trans. Computer-Aided Design, vol. 16, pp. 316-320, Mar. 1997. [9] Analysis of Buck Converters for On-Chip Integration With a Dual Supply Voltage MicroprocessorVolkan Kursun, Siva G. Narendra, Vivek K. De, and Eby G. FriedmanAbstract-An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dualmicroprocessor is demonstrated to be feasible.Index Terms-Buck converter, dc-dc converter, dual supply voltage, high efficiency, integrated inductors, low power, low voltage, modeling of dc-dc converters, monolithic dc-dc conversion, multiple supply voltages, power supply, supply voltage scaling, switching dc-dc converters, voltage regulator.

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Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks. This algorithm can be applied at all levels of a circuit hierarchy, where the internal blocks can represent transistors, cells within an array, or entire modules. This methodology will give an upper bound for the sleep transistor size required to meet any performance constraint. BACKGROUNDMulti-threshold CMOS is an emerging technology that provides high performance and low power operation by utilizing both high and low V t transistors[1][2][3]. By using low V t transistors in the signal path, the supply voltage can be lowered (while still maintaining performance) to reduce switching power dissipation. By reducing V dd , the switching power can be reduced quadratically, but as V t decreases to maintain performance, the subthreshold leakage current will increase exponentially. For ambitious scaling, the increased leakage power can actually dominate the switching power [4]. In many event driven applications, like a processor running an X-server, circuits spend most of their time in an idle state where no computation is being performed. During these "sleep" times, it is very wasteful to have large subthreshold leakage currents. Static power dissipation can be reduced in the sleep mode by using high V t transistors with very low leakage currents to gate the power supply lines for the entire module. Figure 1. MTCMOS circuit structure. V dd Sleep High V t Low V t Logic Device Virtual Ground Module NMOS sleep transistor preferred since lower on resistanceAlthough it is easy to reduce leakage by using a high V t gating device, it is difficult to size the sleep transistor large enough so that performance is maintained. Some initial work on MTCMOS circuits was presented in [5], and it was shown that the sleep transistor can be approximated very closely by a linear resistor that creates a finite voltage drop across the virtual ground node as gates are discharging. This virtual ground bounce causes the internal logic to slow down for two reasons: first, the gate drive is reduced and second, the internal transistor threshold voltages will increase due to the body effect. The worst case delay in an MTCMOS circuit is strongly dependent on the discharge patterns of internal gates, which will cause the virtual ground line to fluctuate depending on discharge patterns through this sleep transistor. The worst case input vector is difficult to predict and can even be different than a vector which exercises a critical path in an ordinary CMOS implementation. As a result, optimal sizing of the sleep transistor for an arbitrary circuit to meet a performance constraint can be difficult. A ...

Technology scaling demands a decrease in both vdd and V, to sustain historical delay reduction, while restraining active power dissipation. Scaling of V, however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two offdevices has smaller leakage current than one offdevice. In this paper we present a model that predicts the scaling nature of this leakage reduction effect. Device measurements are presented to prove the model's accuracy. Use of stack effect for leakage reduction and other implications of this effect are discussed.

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