MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Abstract

Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks. This algorithm can be applied at all levels of a circuit hierarchy, where the internal blocks can represent transistors, cells within an array, or entire modules. This methodology will give an upper bound for the sleep transistor size required to meet any performance constraint. BACKGROUNDMulti-threshold CMOS is an emerging technology that provides high performance and low power operation by utilizing both high and low V t transistors[1][2][3]. By using low V t transistors in the signal path, the supply voltage can be lowered (while still maintaining performance) to reduce switching power dissipation. By reducing V dd , the switching power can be reduced quadratically, but as V t decreases to maintain performance, the subthreshold leakage current will increase exponentially. For ambitious scaling, the increased leakage power can actually dominate the switching power [4]. In many event driven applications, like a processor running an X-server, circuits spend most of their time in an idle state where no computation is being performed. During these "sleep" times, it is very wasteful to have large subthreshold leakage currents. Static power dissipation can be reduced in the sleep mode by using high V t transistors with very low leakage currents to gate the power supply lines for the entire module. Figure 1. MTCMOS circuit structure. V dd Sleep High V t Low V t Logic Device Virtual Ground Module NMOS sleep transistor preferred since lower on resistanceAlthough it is easy to reduce leakage by using a high V t gating device, it is difficult to size the sleep transistor large enough so that performance is maintained. Some initial work on MTCMOS circuits was presented in [5], and it was shown that the sleep transistor can be approximated very closely by a linear resistor that creates a finite voltage drop across the virtual ground node as gates are discharging. This virtual ground bounce causes the internal logic to slow down for two reasons: first, the gate drive is reduced and second, the internal transistor threshold voltages will increase due to the body effect. The worst case delay in an MTCMOS circuit is strongly dependent on the discharge patterns of internal gates, which will cause the virtual ground line to fluctuate depending on discharge patterns through this sleep transistor. The worst case input vector is difficult to predict and can even be different than a vector which exercises a critical path in an ordinary CMOS implementation. As a result, optimal sizing of the sleep transistor for an arbitrary circuit to meet a performance constraint can be difficult. A ...

Novel power –up sequence control for MTCMOS designs

“…The number and size of the transistors used in the power switch fabric determine the voltage drop between the true VDD and the virtual VDD [5]- [7]. This voltage drop degrades circuit performance, and must be kept below a user-specified value.…”

Place and route considerations for voltage interpolated designs

“…Different circuit size granularities have been explored for power gating, although primarily coarse-grain techniques have been applied in industry. Many works have examined issues surrounding power switch sizing, and implemented schemes to accurately assess how much area is required for a given circuit block [11][12][13], by taking into account input patterns and timing criticality of the cells being power gated. In the context of VI, we explore the tradeoffs between circuit size granularities for power gating.…”

Early detection of current hot spots in power gated designs

“…Based on the granularity of the blocks, different sleep transistor networks have been proposed. Module-based sleep transistors are inserted at the root of the power distribution network of large modules [2]. A fine-grained sleep transistor insertion approach is proposed in [3]- [7] where sleep transistors are wired together forming a Distributed Sleep Transistor Network (DSTN).…”