Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Tschanz, James; Kim, Nam Sung; Dighe, Saurabh; Howard, Jason D.; Ruhl, G.; Vanga, Subba Reddy; Narendra, S.; Hoskote, Yatin; Wilson, H.; Lam, Chi-Seng; Shuman, M.; Tokunaga, Carlos; Somasekhar, Dinesh; Tang, Stephen; Finan, D.; Karnik, Tanay; Borkar, Nitin; Kurd, Nasser; De, Vivek

doi:10.1109/isscc.2007.373409

Cited by 168 publications

(89 citation statements)

References 10 publications

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“…• DV S 1 : critical path emulators to track variations [6] [7] • DV S 2 : independent monitoring of variations with individual sensors [8] • DV S 3 : scaling V dd until failure [9] The first method, DV S 1 , uses critical path emulators to mimic on-chip silicon behavior of the critical path. The emulator is typically a delay-chain that mimics the actual critical path.…”

Section: Dynamic Voltage Scaling (Dvs) Overviewmentioning

confidence: 99%

“…It includes a core, V dd droop sensors, thermal sensors, a dynamic adaptive biasing controller (DAB), distributed noise injectors (i.e. to produce variations), body bias generators, and a PLL unit [8]. To boost the performance of the TCP offload accelerator core, various combinations of V dd , frequency, and body bias are adapted to V dd noise, temperature changes, and transistor aging.…”

Section: Dynamic Voltage Scaling (Dvs) Overviewmentioning

confidence: 99%

“…To identify and adapt to variations at low V dd and into the sub-threshold region, three adaptive methods utilized within DVS systems have been shown: critical path emulators to track variations [6] [7], independent monitoring of variations with individual sensors [8], and scaling supply voltage until failure [9]. The first two methods eliminate a portion of the safety margins due to worst-case PVT conditions but are unable to account for on-chip variation and local changes in temperature and voltage.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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Ajoitusvirheentunnistus (TED) mahdollistaa energian kulutuksen vähentämisen mikroprosessoreissa. Tässä diplomityössä on kaksi versiota ajoitusvirheentunnistavasta salvasta (esim. TDTBsubI ja TDTBsubII) ja systeemitason testipiiri (SystemTest), joka käyttää TDTBsub salpaa, mikä on suunniteltu toimimaan kynnysalueen alapuolella. Diplomityö esittelee ensin dynaamisen jännitteen skaalauksen (DVS), koska TED käytetään sellaisissa järjestelmissä. Seuraavaksi esitellään teoriaa kynnysalueen alapuolen suunnittelun haasteista. Sitten esitellään molempien TDTBsub salpojen ja SystemTest-lohkojen suunnittelu. Simulaatiotuloksia esitellään keskittyen operaatiotaajuuteen, energian kulutukseen ja toimintavarmuuteen variaatiot huomioon ottaen. Operoitaessa kynnysalueen alapuolella TDTB-piirillä keskityttiin koon mitoittamiseen ja suunnittelutyyliin. Ennen kaikkea kaikkien komponenttien mitoituksen piti olla suurempi kuin minimi CMOS-tekniikan leveydet. Vaikka mitoittamisella saavutettiin toimintavarmuutta kynnysalueen alapuolella toimittaessa myös energian kulutus kasvoi siellä toimittaessa. Perinteisiä vuotovirtojen vähentäviä mitoitustoimenpiteitä tehtiin suurimmalle osalle komponenteista. Logiikkatyyli on tärkeää kynnysalueen alapuolella operoitaessa. TDTBsubII salvassa uuden tekniikan näytetään antavan systeemitason suorituskykyä. Simulaatioilla näytettiin kuinka ajoitusvirheentunnistus kykeni toimimaan kynnystason alapuolella. TDTBsubI:n ja yhteenlaskun testipiirin piirinkuvio tehtiin 65nm CMOS-prosessilla. TDTBsubII salpaa ei tehty, koska se suunniteltiin piirin määräajan jälkeen. Piiriä tarkasteltaessa osoittautui, että piiri ei toiminut. Piirin toimimattomuus johtui tuotantovaiheessa tapahtuneesta virheestä eikä suunnittelusta. Avainsanat:sub-threshold,weak inversion,low power,low voltage,digital CMOS To operate TDTBsub into sub-threshold, attention was given to sizing and logic style. In general, the sizing of all components was required to be larger than the minimum CMOS width. Although this provided robustness in sub-threshold, the energy consumption in above sub-threshold was much higher. General leakage reduction sizing techniques were also applied to the majority of components. The choice of logic style is important for sub-threshold operation. In the TDTBsubII latch, a new technique is shown to provide system-level capability. Simulations displayed the capability of TED in sub-threshold. The layout of TDTBsubI and an adder test circuit were constructed in 65 nm CMOS. The TDTBsubII latch was not built since it was designed after the chip deadline. Upon inspection of the chip, it was determined to be inoperative. This mistake was a result of the manufacturering process and not the design in this work. Keywords:sub-threshold, weak inversion, low power, low voltage, digital CMOS ii ForewordThe work for this thesis was carried out at the Electronic Circuit Design Laboratory (ECDL) of TKK. The financial support of this project was provided by the Academy of Finland. The project was coordinated with University of Turku ...

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Section: Dynamic Voltage Scaling (Dvs) Overviewmentioning

confidence: 99%

Section: Dynamic Voltage Scaling (Dvs) Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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“…The algorithms can be modified accordingly, to determine the optimal body bias and supply voltage configuration, to overcome the effects of process and thermal variations, and temporal degradation. A practical example of a system that uses the above scheme, and compensates for PVT variations, as well as aging, is seen in a 90nm-based design in [20].…”

Section: A Overview Of the Control Systemsmentioning

confidence: 99%

Body Bias Voltage Computations for Process and Temperature Compensation

Kumar

Kim

Sapatnekar

2008

IEEE Trans. VLSI Syst.

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Abstract-With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation techniques to pull back the chip to the nominal operational region. One such scheme, known as Adaptive Body Bias (ABB), has become extremely effective in ensuring optimal performance or leakage savings. Our work provides a means to efficiently compute the body bias voltages required for ensuring high performance operation in gigascale systems. We provide a CAD perspective for determining the exact amount of bias voltages that can compensate both temperature and process variations. Mathematical models for delay and leakage based on minimal tester measurements are built, and a nonlinear optimization problem is formulated to ensure highest frequency operation under all conditions, and thereby minimize the overall circuit leakage. Three different algorithms are presented and their accuracies and run-times are compared. The algorithms have been applied to a wide range of process and temperature corners, for a 65nm and a 45nm technology node based process. A suitable implementation mechanism has also been outlined.

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“…While [9] demonstrated that ABB could be used to recover the circuit from voltage and temperature variations, as well as aging, our work is the first comprehensive CAD solution to take advantage of the reduction in leakage due to bias temperature instability (BTI). We demonstrate how ABB can be used to maintain the optimal performance of the circuit over its lifetime Ø life , by determining the PMOS and NMOS body bias values (and supply voltage) required at all time points.…”

Section: Introductionmentioning

confidence: 99%

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guardbands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.

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Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Cited by 168 publications

References 10 publications

Sub-threshold operation of a timing error detection latch

Sub-threshold operation of a timing error detection latch

Body Bias Voltage Computations for Process and Temperature Compensation

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

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