Subthreshold leakage modeling and reduction techniques

Kao, J.; Narendra, S.; Chandrakasan, Anantha P.

doi:10.1145/774572.774593

Cited by 181 publications

(109 citation statements)

References 31 publications

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“…Therefore, a leakage current will be generated from Drain to Source although the transistor is in the off state. This is called subthreshold leakage where the gate-source voltage is less than the threshold voltage [4]. The current depends exponentially on the gate-source voltage [9].…”

Section: A Principle Of Leakage In the Pixel Structurementioning

confidence: 99%

“…Since the leakage model has been developed in the last section, this can be solved by the leakage percentage as proposed in (4). Therefore, the improved TPFFC including a new training set selection method based on leakage percentage is as follow: 1) Generate uniform light for training: The basic purpose of training images is to provide an example of the imager response while all the pixels are receiving the same amount of energy.…”

Section: Improved Two Points Ffc Algorithmmentioning

confidence: 99%

“…In the typical pixel structure, the electron well of the pixel is normally connected with a transistor which is in off-state while the photodiode is integrating the light. In the off-state, there exists a leakage current from drain to source of the transistor [4]. In strong light conditions, the leakage is neglected because the signal, i.e.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Leakage Modeling and Flat Field Correction Algorithm for CMOS Hyper Spectral Imaging Sensor

Liu¹,

Mainali²,

Tackand³

et al. 2013

IJMO

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Abstract-In hyper spectral imaging applications, the light power reaching the image sensofr is greatly reduced compared to broadband color image sensors. Consequently, some typical algorithms, such as Flat Field Correction (FFC), are not guaranteed anymore to work in the same way as in their normal operation for broadband color imaging. This is caused by transistor leakage which cannot be neglected anymore. In this paper, we propose a mathematical leakage model based on the basic transistor theory to tag the validity of the sensor response. The model has been validated by comparing the simulation results to measurements of the pixel response of a hyper spectral imager. We also demonstrate that this leakage model is able to select the proper training set for a typical FFC algorithm.Index Terms-Leakage model, transistor leakage, CMOS imager, hyper spectral imaging, flat field correction.

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Section: A Principle Of Leakage In the Pixel Structurementioning

confidence: 99%

Section: Improved Two Points Ffc Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Leakage Modeling and Flat Field Correction Algorithm for CMOS Hyper Spectral Imaging Sensor

Liu¹,

Mainali²,

Tackand³

et al. 2013

IJMO

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“…This technique is also referred to as dual-V th partitioning [24]. Those logic gates that are not part of the critical path are replaced with high-V th transistors to reduce the leakage current by exploiting the excessive slack.…”

Section: Previous Workmentioning

confidence: 99%

Path Specific Register Design to Reduce Standby Power Consumption

Salman

2011

JLPEA

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A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current.

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“…It is known that leakage power may make up 42% of total power at the 90nm technology node [2]. Thus various techniques are proposed to reduce the leakage power from system level down to physical level.…”

Section: Introductionmentioning

confidence: 99%

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

Wang

Liu

Luo

et al. 2006

Lecture Notes in Computer Science

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Abstract. Fine-grain Sleep Transistor Insertion (FGSTI) is an effective leakage reduction method in VLSI design optimization. In this paper, a novel Genetic Algorithm (GA) based FGSTI technique is presented to decide where to put the sleep transistors (ST) when the circuit slowdown is not enough to assign sleep transistors everywhere in the combinational circuits. Penalty based fitness function with a built-in circuit delay calculator is used to meet the performance constraint. Although optimal FGSTI problem is proved to be NP-hard, our method can steadily give a flexible trade-off between runtime and accuracy. Furthermore a Successive Chromosome Initialization method is proposed to reduce the computation complexity when the circuit slowdown is 3% and 5%. Our experimental results show that the GA based FGSTI technique can achieve about 75%, 94% and 97% leakage current saving when the circuit slowdown is 0%, 3% and 5% respectively.

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Subthreshold leakage modeling and reduction techniques

Cited by 181 publications

References 31 publications

Leakage Modeling and Flat Field Correction Algorithm for CMOS Hyper Spectral Imaging Sensor

Leakage Modeling and Flat Field Correction Algorithm for CMOS Hyper Spectral Imaging Sensor

Path Specific Register Design to Reduce Standby Power Consumption

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

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