Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

Hazucha, P.; Karnik, Tanay; Walstra, S.; Bloechel, B.; Tschanz, James; Maiz, J.; Soumyanath, K.; Dermer, G.; Narendra, S.; De, Vivek; Borkar, S.

doi:10.1109/cicc.2003.1249472

Cited by 62 publications

(57 citation statements)

References 5 publications

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“…As for TFs affecting the input node, as discussed in details in Section 7, the HiPeR latch provides high robustness, similarly to the previous solutions in [13,15,16,17,11].…”

Section: Proposed Hiper Latchmentioning

confidence: 78%

“…Soft errors have traditionally been recognized as a problem for high-density memories, because of their small cell size [10], [11]. Error correcting codes (ECCs), in particular single error correcting/double error detecting codes, have been successfully employed to guarantee a satisfactory level of memory reliability.…”

Section: Introductionmentioning

confidence: 99%

“…Some approaches rely on the modification of the latch structure in order to make it robust independently of the hitting particle energy. This is the case of the scheme proposed in [10], referred to as DICE cell, and the latch in [11,15]. These latches make use of two independent feedback loops controlling the output.…”

Section: Introductionmentioning

confidence: 99%

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High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-First a new high performance robust latch (referred to as HiPeR latch) is presented, that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed, that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good tradeoffs in terms of performance, robustness and cost, our proposed latches are particularly suitable to be adopted on critical paths.

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“…As for TFs affecting the input node, as discussed in details in Section 7, the HiPeR latch provides high robustness, similarly to the previous solutions in [13,15,16,17,11].…”

Section: Proposed Hiper Latchmentioning

confidence: 78%

Section: Introductionmentioning

confidence: 99%

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High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

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“…The measurements were used to calibrate an SER model that was later validated by independent SER measurements on SRAM [64]. The model is now used to estimate the SER of products and to optimize designs for reduced SER [39], [73].…”

Section: Application To a 90nm Cmos Processmentioning

confidence: 99%

Characterization of soft errors caused by single event upsets in CMOS processes

Karnik

Hazucha

2004

IEEE Trans.Dependable and Secure Comput.

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437

209

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Abstract-Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

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“…However, soft-error problem becomes more critical in subthreshold SRAMs [6]. Soft-error rate (SER) increases by 18% for every 10% reduction of V DD [7,8]. Bit-interleaving technique is a good way to enhance soft-error immunity by physically interleaving bits of data from different words.…”

Section: Introductionmentioning

confidence: 99%

A 0.2 V–1.8 V 8T SRAM with Bit-interleaving Capability

Zhao

Fan

Chen

et al. 2014

IEICE Electron. Express

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An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-bodybiased 8T cell. Also, a write driver is presented to enable the bitinterleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fulfils the functionality under supply voltage from 1.8 V to 0.3 V (0.2 V when the write wordline is boosted to 0.36 V) and the total power is reduced by four times of magnitude.

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Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

Cited by 62 publications

References 5 publications

High-Performance Robust Latches

High-Performance Robust Latches

Characterization of soft errors caused by single event upsets in CMOS processes

A 0.2 V–1.8 V 8T SRAM with Bit-interleaving Capability

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