Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Tschanz, Jim; Narendra, S.; Ye, Yibin; Bloechel, B.; Borkar, S.; De, Vivek

doi:10.1109/isscc.2003.1234225

Cited by 84 publications

(78 citation statements)

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“…However as the technology scales down, more aggressive leakage reduction techniques are required. As a promising technique, runtime power gating (RTPG) has drawn more attention recently [5][6][7][8][9][10]. As shown in Figure 1, RTPG turns off the power gate once it detects sufficient idleness in circuit workload, even when the circuit is in the active mode.…”

Section: Introductionmentioning

confidence: 99%

Accurate energy breakeven time estimation for run-time power gating

Jone

Vemuri

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been proposed as a critical figure of merit of RTPG. Our research introduces the definition of average EBT in a runtime environment. We develop a method to estimate the average EBT for any given circuit block, considering the impact of circuit states. HSPICE simulation results on ISCAS85 benchmark circuits show that the average EBT model has on the average 1.8% error. The CAD tool implemented based on the model can perform fast estimations with a speedup of 3000× over HSPICE.

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Section: Introductionmentioning

confidence: 99%

Accurate energy breakeven time estimation for run-time power gating

Jone

Vemuri

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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“…As leakage is becoming a growing concern in the current microprocessor designs, several leakage control mechanisms have been studied [9][11] [19] [20]. All these mechanisms try to reduce leakage when the circuit is in idle state.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Many leakage control techniques have been studied [9][11] [19] [20], power gating being one of the most prominent ones. Power gating cuts the supply voltage to the idle functional units, resulting in leakage energy savings.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment

Kumar

Martínez

González

2013

2013 25th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Leakage power is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this power. Therefore, reducing functional unit leakage has received much attention in the recent years. Power gating is one of the most widely used techniques to minimize leakage energy. Power gating turns off the functional units during the idle periods to reduce the leakage. Therefore, the amount of leakage energy savings is directly proportional to the idle time duration. This paper focuses on increasing the idle interval for the higher SIMD lanes. The applications are profiled dynamically, in a HW/SW co-designed environment, to find the higher SIMD lanes usage pattern. If the higher lanes need to be turned-on for small time periods, the corresponding portion of the code is devectorized to keep the higher lanes off. The devectorized code is executed on the lowest SIMD lane. Our experimental results show average SIMD accelerator energy savings of 12% and 24% relative to power gating, for SPECFP2006 and Physicsbench. Moreover, the slowdown caused due to devectorization is less than 1%.

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“…Supply and threshold voltage optimization, in the context of low power CMOS circuit design, is an area of active current research; see, e.g., Anis et al (2003), Chabini et al (2003), Chen et al (2001), Kao et al (2002), Pant et al (2001), and Srivastava and Sylvester (2004). Many approaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages (Chang and Pedram 1997;Jung et al 2003;Kim et al 2003a, b;Krishnamurthy and Carley 1997;Marković et al 2004;Sirichotiyakul et al 2002;Srivastava and Sylvester 2004;Yeh et al 2001), multiple threshold CMOS (MTCMOS) (Anis et al 2002(Anis et al , 2003Calhoun et al 2004;Kao and Chandrakasan 2000), variable threshold CMOS (VTCMOS) via adaptive body biasing (Im et al 2003, Kao et al 2002, Tschanz et al 2003, Yang et al 1997, dynamic threshold CMOS (DTCMOS) (Assaderaghi et al 1997), joint device sizing and V dd /V th assignment (Augsburger and Nikolić 2002a, b;Chen and Sarrafzadeh 2002;Hung et al 2004;Ketkar and Sapatnekar 2002;Karnik et al 2002;Liu et al 2004;Nguyen et al 2003;Pant et al 2001), dynamic frequency scaling (Lu et al 2002), supply voltage scaling (Bellaouar et al 1998), and transistor stacking (Johnson et al 2002.…”

Section: Supply and Threshold Voltage Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

151

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Cited by 84 publications

References 0 publications

Accurate energy breakeven time estimation for run-time power gating

Accurate energy breakeven time estimation for run-time power gating

Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment

Digital Circuit Optimization via Geometric Programming

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