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Dual threshold technique has been proposed to reduce leakage power in low v oltage and low p o w er circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical paths to maintain the performance. Mixed-Vth MVT static CMOS design technique allows di erent thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Di erent MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistorlevel threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20 more leakage reduction compared to the corresponding gate-level dual threshold technique.

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Joint ootimizations of dual-VT allocation and transistor sizing reduce'low-VT usage by 36%-45% and leakage power by 20% with minimal impact on total active power and die area.An enhancement of the optimum design allows processor frequency to he increased efficiently during manufacturing.