Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

Hazucha, P.; Karnik, Tanay; Maiz, J.; Walstra, S.; Bloechel, B.; Tschanz, James; Dermer, G.; Hareland, S.A.; Armstrong, Peter; Borkar, S.

doi:10.1109/iedm.2003.1269336

Cited by 91 publications

(58 citation statements)

References 3 publications

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“…According to [7], SER increases by 18% for every 10% reduction and hence, SER in 0.3 V can be 8.6X higher than that in 1.2 V . Low gate capacitance of weak inversion makes the problem worse due to the reduction of critical charge (Qc) [8].…”

Section: Efficient Bit-interleaving For Soft-error Immunitymentioning

confidence: 99%

“…However, the single-end 8T or 10T SRAMs cannot efficiently deal with multiple bit soft-errors, which can have large impact on SRAM operation in the subthreshold region. As supply power scales down, soft-error rate (SER) increases [7]. Moreover, in the subthreshold region, critical charge [8] is also reduced due to low gate capacitance and hence, SER can be much larger than that in the superthreshold region.…”

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confidence: 99%

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A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Chang

Kim

Park

et al. 2009

IEEE J. Solid-State Circuits

391

205

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Abstract-Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing.

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Section: Efficient Bit-interleaving For Soft-error Immunitymentioning

confidence: 99%

mentioning

confidence: 99%

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Chang

Kim

Park

et al. 2009

IEEE J. Solid-State Circuits

391

205

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show abstract

“…On the other hand, soft error immunity of subthreshold circuits has become a concern because the ultra-low voltage operation reduces the energy required to cause upsets [3], [4]. Especially, the soft error rate (SER) in SRAM, which often characterize the SER of the entire circuit, must be carefully examined before adopting subthreshold circuits for practical applications.According to [5], the neutron-induced SER in SRAM increases by 18% for every 10% reduction in the supply voltage. Reference [6] reports a trend that decrease in the supply voltage makes the alpha-particle-induced SER dominant in SRAM.…”

mentioning

confidence: 99%

Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM

Fuketa

Hashimoto

Mitsuyama

et al. 2010

2010 IEEE International Reliability Physics Symposium

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Abstract-This paper presents measurement results of alphaparticle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 V to 0.3 V. We reveal that the soft error rate (SER) at 0.3 V is eight times higher than SER at 1.0 V, and the ratio of MCUs to the total upsets increases as the supply voltage decreases. The SER and ratio of MCUs with body-biasing are also described. In addition, we investigate an impact of manufacturing variability on the soft error immunity of each memory cell. In our measurement, a distinct influence of manufacturing variability is not observed even in subthreshold region. I. INTRODUCTIONSubthreshold circuits, which operate at a lower supply voltage than threshold voltage, are expected to be used for ultralow power applications, such as a sensor-node processor [1], [2]. On the other hand, soft error immunity of subthreshold circuits has become a concern because the ultra-low voltage operation reduces the energy required to cause upsets [3], [4]. Especially, the soft error rate (SER) in SRAM, which often characterize the SER of the entire circuit, must be carefully examined before adopting subthreshold circuits for practical applications.According to [5], the neutron-induced SER in SRAM increases by 18% for every 10% reduction in the supply voltage. Reference [6] reports a trend that decrease in the supply voltage makes the alpha-particle-induced SER dominant in SRAM. However, these measurements were just performed between the nominal supply voltage and 0.8 V. As for soft errors in subthreshold region, single event transient (SET) was recently analyzed with ring oscillators in [3]. On the other hand, the SRAM SER in subthreshold region has not been measured as far as the authors know. This paper is the first work to measure the alpha-particleinduced SER in subthreshold region using a newly designed 65-nm 10T SRAM. Measurement results show that 0.3 V operation increases SER eightfold compared to 1.0 V. In addition, information on frequency of multiple cell upsets (MCUs) is important for error prevention using error checking and correction (ECC) technique. In this paper, we also investigate MCUs in subthreshold region. We reveal that although the ratio of MCUs to the total upsets remarkably increases at lower voltage, conventional ECC technique is still effective in our 10T subthreshold SRAM. Additionally, the dependency of SER on body-bias is evaluated, and measurement results indicate that the SER and the ratio of MCUs are less sensitive to the body-bias voltage when the supply voltage is 0.4 V.

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“…According to [7], the neutron-induced SER in SRAM increases by 18% for every 10% reduction in the supply voltage. Tosaka et al have reported a trend in which a decrease in the supply voltage makes the alpha-particle-induced SER dominant in SRAM [8].…”

mentioning

confidence: 99%

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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Abstract-This paper presents measurement results of alphaparticle-induced soft errors and multiple-cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 to 0.3 V. We reveal that the soft-error rate (SER) at 0.3 V is six times higher than that at 1.0 V and the MCU rate significantly increases in the subthreshold region. To investigate the reason for the MCU increase, the dependences of the MCU rate on the body-bias voltage and the distance between well ties are examined, and we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing. In addition, the dependence of the variation in the soft-error immunity of each memory cell on the supply voltage is examined, since SRAMs operating in the subthreshold region are sensitive to manufacturing variability. Measurement results indicate that the number of soft errors in each memory cell varies cell by cell, whereas the cause of the variation is explained by the spatial randomness of alpha-particle hits, and a distinct influence of manufacturing variability is not observed even in the subthreshold region.Index Terms-Alpha-particle-induced soft error, multiple-cell upset (MCU), soft-error rate (SER), subthreshold circuit.

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Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

Cited by 91 publications

References 3 publications

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

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