Abstract-Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing.

Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H‐TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H‐TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (VOUT) does not fully swing from VDD to GND. A new H‐TR device structure that consists of a dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene (DNTT) layer stacked on a PTCDI‐C13 layer is presented. Due to the continuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p‐type off/p‐type subthreshold region /NTC/ p‐type on. As a result, it has a very high on/off current ratio (≈105) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H‐TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full VDD‐to‐GND swing of VOUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis‐free operation due to the use of a hydrophobic gate dielectric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time.

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Abstract-Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing.

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wileyonlinelibrary.comthe solution-processable organic semiconductors, small molecular semiconductors such as 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-Pentacene) [6][7][8][9][10] and difluoro-bis(triethylsilylethynyl) anthradithiophene (diF-TES-ADT) [11][12][13][14] have attracted much attention because of their relatively high fi eld-effect mobility and solution processability. One way to further improve performance characteristics of the smallmolecule OFET devices is to blend the semiconducting materials with one or more insulating polymer materials. [ 11,15 ] Initially investigated by Sirringhaus and co-workers that used a two-component blend based on polythiophenes and different insulating polymers for OFET applications, [ 16 ] this approach has been also applied successfully to small-molecule organic semiconductors, [ 11 ] blended with insulating [17][18][19][20] or other semiconducting polymers. [ 21 ] Recently, high mobility OFETs have been demonstrated with a TIPS-Pentacene blend [ 9 ] and with a diF-TES-ADT blend. [ 13 ] Because charge carriers in OFETs are mostly transported in a direction parallel to the substrate, the formation of a vertically phase-separated bilayer structure can lead to higher performances of the transistors. Factors such as the surface tension of each component, [ 19 ] the solvent evaporation rate, [ 9 ] molecular weight of insulating polymer, [ 22 ] and the characteristics of the substrate [ 23,24 ] should be considered for the sharp vertical phase separation, so the choice of adequate insulating polymers is quite limited and the postannealing processes are sometimes needed. [ 20,22,23 ] Furthermore, there is inevitably the intermixed area with thickness of tens to hundreds of nanometers between semiconductor and insulating polymer layers. This will presumably result in the rough conduction channel if the interface between semiconductor and insulating polymer is used as a conduction channel (interface channel), so the carrier mobilities become lower than ideal values. For this reason, a strategy to use polymers only as a template and to use the opposite semiconducting side from the interface as a conduction channel (top channel) has been suggested. [ 11 ] Kippelen and co-workers reported that the top channel exhibited the 2.0-4.7 times higher mobilities than the interface channel in the case of TIPS-Pentacene OFETs.Here, a highly crystalline and self-assembled 6,13-bis(triisopropylsilyleth ynyl) pentacene (TIPS-Pentacene) thin fi lms formed by simple spin-coating for the fabrication of high-performance solution-processed organic fi eldeffect transistors (OFETs) are reported. Rather than using semiconducting organic small-molecule-insulating polymer blends for an active layer of an organic transistor, TIPS-Pentacene organic semiconductor is separately selfassembled on partially crosslinked poly-4-vinylphenol:poly(melamine-co -formaldehyde) (PVP:PMF) gate dielectric, which results in a vertically segregated semiconductor-dielectric fi lm with millimeter-sized spherulite-cr...

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