Abstract-We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter-and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.

Input vector control has been used to minimize the leakage power consumption of a circuit in sleep state [1]. In this paper, we present a novel heuristic for determining a low leakage vector to be applied to a circuit in sleep state. The heuristic is a greedy search based on the controllability of nodes in the circuit and uses the functional dependencies among cells in the circuit to guide the search. Results on a set of ISCAS and MCNC benchmark circuits show that in all cases our heuristic returns a vector having a leakage within 5% of that of the vector obtained using an extensive random search, with orders of magnitude improvement in computational speed.

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The stability and performance characteristics of Static Random Access Memories (SRAMs) are known to degrade with time due to the impact of Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)). In this work, we provide insights into relative sensitivities of these phenomena on speed and stability of SRAM cells. Relative impact on access time, stability, and tolerability of one phenomenon over another has been studied for different application specific (high-performance or low-power) SRAM cells. We show that high-performance SRAM cells should have lower V T drift due to PBTI compared with dense cells to contain READ stability and access time. Further, worst-case static stress poses tighter process constraints compared with alternating stress.

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