IBM POWER7+ design for higher frequency at fixed power

Zyuban, Victor; Taylor, Scott A.; Christensen, Björn; Hall, Annika; González, Christopher; Friedrich, Joshua; Clougherty, F.; Tetzloff, J.; Rao, Rahul

doi:10.1147/jrd.2013.2279597

Cited by 16 publications

(16 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, IBM's 45-nm Power7 processor had a 32 MB LLC [29]; the 32-nm Power7+ processor had an 80 MB LLC [30]; and the 22-nm Power8 processor had a 96 MB LLC [31]. LLC size in GPUs is also on the rise [32].…”

Section: Motivation Behind the Design Of Destinymentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

View full text Add to dashboard Cite

Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

show abstract

Section: Motivation Behind the Design Of Destinymentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

View full text Add to dashboard Cite

show abstract

“…This one case study is insufficient to answer the question whether heterogeneous processors will guarantee the superiority over conventional homogeneous processors, particularly in the domain of embedded systems. In our analysis, we measure the Blue Gene/Q processor that includes 16 user cores (and 2 additional cores for system operations and spare, respectively) [9] and POWER7+ processor comprised of 8 complex cores with 4-way SMT per core [17]. Such hardware availability enables us to explore more diverse composition of heterogeneous processors and compare them with the existing homogeneous platforms.…”

Section: Related Workmentioning

confidence: 99%

“…However, SMT is a commonly found feature in server-class cores and known to boost throughput efficiency. For instance, IBM POWER7 and POWER7+ processors support 4-way SMT per core [8,17]. By utilizing 4-way SMT, the complex cores in homogeneous design could ostensibly provide as much parallel speed-up as the simple cores of heterogeneous processor without the SMT feature.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency

Song

Buyuktosunoglu

Cher

et al. 2016

Proceedings of the 2016 International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

It is generally perceived that heterogeneous multicore processors will provide better performance and power efficiency over conventional homogeneous cores. However, heterogeneity can also be achieved within a homogeneous core design, instantiated under different voltage-frequency settings or per-core simultaneous multitreading (SMT) modes. In this paper, we pursue an architectural study motivated by the question, "Can we get by with a single, complex SMT-equipped core design that can operate at different voltage-frequency points? Or, is it mandatory to invest into two different core types, one complex and the other simple?" We propose a systematic, measurement-driven methodology to evaluate processor heterogeneity options. Our analysis particularly focuses on the domain of real-time constrained embedded processors. The study is based on a direct measurement of two real processors; one that uses simple in-order cores, and another that uses complex out-of-order cores. The effect of heterogeneous core composition (consisting of complex and simple cores in the same chip) is analytically projected from measurements gleaned from the two different systems. Our analysis yields new interesting insights. When dealing with two core types without SMT enabled, true core heterogeneity does not necessarily provide better performance or power efficiency under area and power constraints. If the complex-core homogeneous processor invokes SMT, it outperforms true heterogeneity by offering 28% better power efficiency, assuming that simple cores in the heterogeneous system operate only in single-threaded mode without SMT capability. If the small cores employ SMT, true heterogeneity yields 32% better power efficiency than the homogeneous processor with SMT.

show abstract

“…The ability to create process, voltage and temperature (PVT) independent standard cell power contributor abstracts and the ability to create PVTindependent gate level power abstracts for IP blocks, and its use for enabling efficient multi-corner hierarchical chip power analysis was discussed by Dhanwada et al [18,16]. The accuracy of the detailed reference chip power analysis tool chain was validated against POWER7+ microprocessor hardware power measurements for a range of unique hardware parts, voltage and temperature conditions [16,19]. The guiding principles of the methodology are as follows: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Detailed Pre-silicon Power Modeling Referencementioning

confidence: 99%

Empirically derived abstractions in uncore power modeling for a server-class processor chip

Jacobson

Joseph

Parikh

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

Early-stage power modeling is an essential aspect of the process of defining efficient, yet high-performance microarchitectures. Presilicon power modeling has been an active area of research and development for well over a decade, although primarily focused on the processor cores. In this paper, we examine the challenge of developing practical abstractions in uncore power modeling in an industrial setting. We report a systematic methodology of abstractions in modeling with a focus on key uncore elements of the POWER8 TM processor chip from IBM. The results show that the active power of these uncore elements can be modeled with acceptable levels of precision, by: (a) using just a few activity markers: e.g. reads, writes, retries and snoops; and (b) using a small set of systematically crafted microbenchmark stress test cases to measure the activity frequencies on a detailed, cycle-and latch-accurate RTL reference model.

show abstract

IBM POWER7+ design for higher frequency at fixed power

Cited by 16 publications

References 12 publications

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency

Empirically derived abstractions in uncore power modeling for a server-class processor chip

Contact Info

Product

Resources

About