Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

Empirically derived abstractions in uncore power modeling for a server-class processor chip

“…This very accurate contributor based power modeling framework forms the reference point in our power abstraction work. The ability to create process, voltage and temperature (PVT) independent standard cell power contributor abstracts and the ability to create PVTindependent gate level power abstracts for IP blocks, and its use for enabling efficient multi-corner hierarchical chip power analysis was discussed by Dhanwada et al [18,16]. The accuracy of the detailed reference chip power analysis tool chain was validated against POWER7+ microprocessor hardware power measurements for a range of unique hardware parts, voltage and temperature conditions [16,19].…”

“…The ability to create process, voltage and temperature (PVT) independent standard cell power contributor abstracts and the ability to create PVTindependent gate level power abstracts for IP blocks, and its use for enabling efficient multi-corner hierarchical chip power analysis was discussed by Dhanwada et al [18,16]. The accuracy of the detailed reference chip power analysis tool chain was validated against POWER7+ microprocessor hardware power measurements for a range of unique hardware parts, voltage and temperature conditions [16,19]. The guiding principles of the methodology are as follows: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

“…Leakage power is calculated by the reference power tool chain by other means [16,18], driven by estimates of total gate width, supply voltage, threshold voltage, and "sort point" information available through separate technology-specific analysis toolsets.…”

“…The RTL switching data, the standard cell power abstracts, the IP block power abstracts, and chip netlist are input to a chip level power modeling and analysis tool [16], and power is computed for each workload for a range of different corners.…”

Bridging high performance and low power in processor design

“…Another important aspect of simultaneous gate sizing and threshold voltage assignment, which often does not get enough attention in literature, is the critical role of accurate work load analysis and circuit activity analysis [8]. For example, given two identical gates in the netlist, one is a control signal that rarely switches while the second is a data signal that changes value during 30% of the clock cycles, we would use a larger cell with higher threshold voltage for the first gate and use a smaller cell with lower threshold voltage for the second gate.…”