Reliability of logic circuits is emerging as an important concern in scaled electronic technologies. Reliability analysis of logic circuits is computationally complex because of the exponential number of inputs, combinations, and correlations in gate failures. This paper presents three accurate and scalable algorithms for reliability analysis of logic circuits. The first algorithm, called observability-based reliability analysis, provides a closedform expression for reliability and is accurate when single gate failures are dominant in a logic circuit. The second algorithm, called single-pass reliability analysis, computes reliability in a single topological walk through the logic circuit. It computes the exact reliability for circuits without reconvergent fan-out, even in the presence of multiple gate failures. The algorithm can also handle circuits with reconvergent fan-out with high accuracy using correlation coefficients as described in this paper. The third algorithm, called maximum-k gate failure reliability analysis, allows a constraint on the maximum number (k) of gates that can fail simultaneously in a logic circuit. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed algorithms.
This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performancearea trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise output logic level. Besides having the best performance-area trade-off our approach, unlike existing techniques, can (i) handle more complex constraints such as maximum node fanout or wirelength that impact the performance/area of a design and (ii) generate several feasible solutions that minimize the objective function. Generating several optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are difficult to model as constraints during logic synthesis. Experimental results demonstrate that our approach improves performance by 3% and area by 9% over even a 64-bit full custom designed adder implemented in an industrial highperformance design.
We present a semi-analytical model incorporating the effects of edge bond relaxation, the third nearest neighbor interactions, and edge scattering in graphene nanoribbon fi eld-effect transistors (GNRFETs) with armchair-edge GNR (AGNR) channels. Unlike carbon nanotubes (CNTs) which do not have edges, the existence of edges in the AGNRs has a signifi cant effect on the quantum capacitance and ballistic I V characteristics of GNRFETs. For an AGNR with an index of m=3p, the band gap decreases and the ON current increases whereas for an AGNR with an index of m=3p+1, the quantum capacitance increases and the ON current decreases. The effect of edge scattering, which reduces the ON current, is also included in the model.
KEYWORDSGraphene nanoribbon field-effect transistor, edge bond relaxation, third nearest neighbor interaction, edge scattering
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale processing and fabrication. This paper combines atomistic quantum transport modeling with circuit simulation to perform technology exploration for GNRFET circuits. A quantitative study of the effects of variations and defects on the performance and reliability of GNRFET circuits is also presented. Simulation results indicate that whereas GNR-FET circuits promise higher performance, lower energy consumption, and comparable reliability at similar operating points to scaled CMOS circuits, they are more susceptible to variations and defects. The results also motivate significant engineering, modeling, and simulation challenges facing the device and CAD communities involved in graphene electronics research.
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